奈米SONOS元件內單電子效應、可靠性物理及創新研究

Abstract

非揮發性記憶體技術，隨著各種新式電子產品應用與龐大需求，已邁入100Gb 儲存之奈米世 代。在各種研發之非揮發性記憶體技術(例如, SONOS, PCM, RRAM,…)中，SONOS 已被公認為最 具可能取代傳統浮動閘極快閃式元件之下一世代記憶體技術。目前SONOS 元件已微縮至奈米尺 度, NOR-type SONOS 已微縮至50 奈米，二位元儲存，而NAND-type SONOS 已達42 奈米，隨著 技術繼續演進，無論在元件物理，元件結構與材料，新式操作方法及記憶體架構各方面，均將面 臨重大挑戰。本計劃將針對奈米SONOS 微縮時之新的物理機制與效應及創新方法，進行為期三 年之研究，內容將涵蓋基本元件理論，元件雜訊random telegraph noise(RTN)，單電子效應及其隨 機特性，蒙地卡羅電子傳輸模擬，及新式元件結構與記憶體架構。主要研究議題，敘述如下； 在 NOR-type SONOS 方面，由於採用熱電子寫入，以致於寫入時操作電壓無法低於3.5V 而 限制閘極長度之微縮。在本計劃，吾人將利用在奈米尺度電子呈現之非平衡傳輸現象，提出一種 新的熱電子操作方式，可將寫入時的操作電壓降至2.5V 以下。NOR-type SONOS 微縮時，另一物 理限制為熱電子寫入時，會經由二次電子(secondary hot electron)之產生而在鄰近元件造成干擾 (program disturb)，此種效應在bitline 微縮時，將愈益明顯，吾人將利用蒙地卡羅模擬研究此種機 制並試圖提出解決方法。此外，當元件微縮時，單一電子效應將更為顯著，單單一顆介面電荷 (interface charge)或儲存電荷(nitride charge)釋放即可能造成讀取錯誤，前者即為RTN，已被廣泛視 為40 奈米以下NAND Flash 之主要可靠性議題。而後者尚未有人報導，吾人將建立一量測技術， 以測量此種單電子效應，觀察其隨機性，並進行理論研究，藉由3D 數值模擬，建立此種單電子 效應之統計模型並決定採用error code correction 時所需位元數。吾人將探討此種單電子效應與元 件結構之關係，並提出一具有高度對稱性之元件結構，以降低此種單電子效應所造成讀取錯誤之 機率。

As non-volatile memory (NVM) is moving rapidly into 100 Gb era, conventional floating gate flash memory suffers from serious coupling issues between cells, thus limiting its further scaling beyond 30nm. Among various alternative NVM technologies (SONOS, PCM, RRAM, ..), SONOS flash is generally considered to be the most promising technology for next-generation NVM. Currently, the SONOS technology node is 50nm for 2-bit storage NOR Flash and 42nm for NAND Flash. As the technology further advances, considerable challenges in cell operation principle, cell structures, materials and reliability physics will be encountered. This project will explore new phenomena, limiting physical mechanisms and innovations of the SONOS technology in scaling. The scope of this research includes single charge phenomena and stochastic process, random telegraph noise (RTN) characterization and 3D simulation, non-equilibrium transport and Monte Carlo simulation, new cell structures and operational principle. Major research topics are described below. For NOR-type SONOS by using hot electron programming, a large drain-to-source voltage Vds (~3.5V) is required for electrons to surmount the SiO2/Si barrier (i.e., 3.1eV). As gate length is reduced, channel punch-through caused by a large Vds becomes a limiting constraint in SONOS scaling. To make a breakthrough, we propose a new hot electron programming method by taking advantage of electron non-equilibrium transport in nano-meter scale devices. In our method, program Vds can be reduced to 2.5V. Besides, we observe a new hot electron program disturb in bit-line scaling, which is attributed to impact ionization-generated secondary hot electrons during programming. A multi-step Monte Carlo simulation will be performed to explore the disturb mechanism. New cell structures to alleviate the disturb will be investigated. In addition, single charge effects are becoming more prominent as devices are further scaled. A single interface (oxide) charge emission or a single program (nitride) charge loss may induce a large fluctuation in read current and cause a read failure. The former has been recognized as random telegraph noise and has been widely accepted as a major failure mechanism in flash memory beyond 40 nm node. The latter has not been published yet. In this project, we will establish a measurement method based on our paper at 2005 VLSI Symp. on Tech. (Best Student Paper Award) to characterize individual program charge retention times, their locations and corresponding changes in read current. We will perform 3D simulation to study current-path percolation effect and develop a statistical model for the retention Vt distribution. New SONOS cells with higher degree of symmetry in programmed charge distributions, for example, (nano-wire SONOS or rounded-corner FinFET SONOS) will be studied, which is expected to have reduced single charge effects (i.e., smaller RTN and Vt loss tail).