三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析(I)

Abstract

本計畫的目的為使用奈米碳管與鎳奈米線材料之矽晶直通孔(TSV)示範三維積體電路測試結構並且建立熱傳導模型、應力分析。本計畫的核心在於將所有相關3D IC製程整合，並至成為一可操作測試的元件結構。首先，矽晶直通孔之製程參數建立包括其準直式蝕刻、蝕刻速率與角度間變異、高深寬比低粗糙度蝕刻等對於後續填孔洞是必須的。再來，設計測試架構平台提供後續製程包括奈米碳管、鎳奈米線之填充，熱模擬分析及應力測試。此測試平台的設計為面對面晶圓銅接合、上層晶圓磨薄、矽晶直通孔(TSV) 蝕刻並且能在實驗室環境下量測。最後，測試結構的電性分析、利用穿透式電子顯微鏡探討側邊架構的填充的品質分析。此外，熱傳在三維積體電路架構下，其熱堆積問題必然會更加嚴重，必須建立其熱傳導模型才可分析不同圖型、材料下矽直通孔去改善熱堆積在三維積體電路的議題。同時，在此之應力分析探討於銅-銅、奈米碳管-催化金屬及接面金屬、鎳-銅接面在不同矽直通孔密度與維度下之變異。建立最佳製程參數流程後，由相關子計畫負責提供符合可在三維積體電路之薄膜電晶體，經過電路布局設計，互相整合成朝向具高散熱性、高穩定性高品質之三維電路應用於未來顯示科技。

The objectives of this project are to demonstrate 3D IC test structures for the utilization of CNT-growth and nickel nanowire growth in through silicon via (TSV), and to establish thermal conductivity model and stress analysis. First of all, it is significant to set up these parameters: collimated etching, variation with etch rate and angle and high aspect ratio with low roughness for subsequent filling TSV. Second, we design the test structure with integrating key technologies, including carbon nanotube (CNT) and nickel nanowire-filled TSV and thermal conductivity simulation and stress analysis. The test structure is fabricated with 3D IC key technologies, including face to face bonding, top wafer thinning, bottom hole via opening, TSV with insulator and seed layer deposition, and it could be measured in lab environment. In the last, the test structure will be analyzed the electrical performances and the material qualities. Furthermore, heat always is an important issue in traditional 2D circuit. This issue definitely becomes worst in 3D IC stacking. Therefore, it is important to establish thermal conductivity model and analyze by various shape of pattern and diameter of TSV to solve the issue. Simultaneously, both industries and academia have concerns with stable reliability of 3D IC structures. The stress analysis will provide the results of contact surfaces and interfaces in the test structure, including variation in Cu-Cu interface, CNT-contact metal, Ni-Cu interface and in variable density and diameter of TSV. After optimizing process flow, we will combine CNT and thin film transistor (TFT), and design a test circuit. Finally, the demonstration of 3D IC we are going to fabricate can provide high performance of thermal dissipation and stable reliability in the future display technology.