Title: 高性能混合訊號式發收機積體電路---子計畫III:高速雙絞線網路發收機單晶片系統
High-Speed Twisted-Pair Network Transceiver System on a Chip
Authors: 吳介琮
WU JIEH-TSORNG
交通大學電子工程系
Keywords: 收發器;單晶片系統;數位類比混合式積體電路;十億位元乙太網路;Transceiver;System-on-a-chip (SOC);Mixed-signal integrated circuit;Gigabit ethernet
Issue Date: 2000
Gov't Doc #: NSC89-2215-E009-066
URI: http://hdl.handle.net/11536/100527
https://www.grb.gov.tw/search/planDetail?id=542658&docId=99734
Appears in Collections:Research Plans