標題: 具前瞻性綠能功能之DOT/EEG/EKG腦心健康照護系統晶片暨嵌入式系統關鍵技術
Advanced Green Energy DOT/EEG/ECG Heart-Brain System on Chip and Embedded Systems for Integrated Brain-Heart Health Care Systems Key Technology
作者: 方偉騏
Fang Wai-Chi
國立交通大學電子工程學系及電子研究所
關鍵字: 可攜式生醫訊號處理系統;腦波;心電圖;擴散光學斷層掃描;系統晶片設計;嵌入式系統設計;低功耗電路設計;腦心照護系統
公開日期: 2010
摘要: 本計畫將提出具前瞻性綠能功能之EEG/ECG/DOT 腦心健康照護系統晶片暨嵌入式系統關鍵技術,透過與美國加州大學聖地牙哥分校神經計算研究所進行技術交流與合作研究,共同研發此系統。此系統包含前端感測電路,將低雜訊前端類比所測得之腦、心臟波及擴散光信號,分別輸入至改良型8/12/16/32通道獨立成份分析引擎、1/12導心電圖分析系統和擴散光學斷層掃描系統,並將信號傳送至資料探勘分析系統以及心臟波、三維腦波與腦影像顯示平台。其中為達到極低功率消耗及高可攜性的目標,本計畫將對系統各部份進行功耗分析,並利用Cadence工具及研發團隊自主設計之極低功率元件庫使晶片達到最低功耗的特性有效提升前端生醫感測系統的可攜性及可穿戴性,並且使用高階封裝技術有效減少晶片體積、改善可靠度及測試品質、並達到異質整合成果。本系統也透過藍芽傳輸模組將初步分離的信號,傳送至資料探勘分析系統,並診斷病患身體健康狀況,然後將腦波、心臟波和組織係數重建訊號傳送至後端顯示與介面嵌入式系統進行三維腦神經信號重建、心電圖檢測和組織重建影像,此三維成像引擎中的幾何子系統及光柵子系統在賽靈思的元件可程式邏輯閘陣列平台上將以軟/硬體協作之方式實現,本計畫也將以純硬體智財方實現到該平台之上。結果將在元件可程式邏輯閘陣列系統輸出至液晶顯示器螢幕,或是以可攜式裝置(如手機/掌上電腦)作為媒介呈現,驗證功能後我們將會進一步以專用集成電路流程實現該設計。
Advanced key technology development for mobile brain-heart health care systems based on energy-aware EEG/ECG/DOT system-on-chip designs and integrated embedded systems is proposed in this proposal. In this project, Swartz Center for Computational Neuroscience of University of California, San Diego and our group will have some technological exchanges and cooperation research on this topic. This advanced system will include a front-end module: low noise analog sensing circuits, adjustable 8/12/16/32-channel EEG processing unit, adjustable 1/12-lead ECG processing unit, portable DOT processor, data mining analysis system and the back-end 3D display platform for EEG/ECG/DOT analyzed results. In order to build a portable and ultra low power system, we add an ultra low noise analog sensing circuit in the front-end circuits. Via this advanced front-end circuit, the measured signals of EEG, ECG and DOT are sent into the advanced Independent Component Analysis, ECG systems and CW-DOT system. In this project, we perform power analysis on each part of the advanced system with the ultra low power cell library designed by our group and Cadence ultra low power EDA tools to reach the goal of building ultra low power consumption systems. In addition, we take advantage of the advanced package technology to reduce the volume of the chip and improve the reliability and testability, then reach the goal of heterogeneous integration. Finally, the front-end and back-end module communicate with each other via the Bluetooth module, and the 3D imaging engine based on Geometry subsystem and Raster subsystem which is implemented on Xilinx FPGA platform. In this project, we will implement this structure by hardware IP, and the separated bio-signals can be shown on the LCD monitor or portable devices (e.g. cell phone/PDA).
官方說明文件#: NSC99-2220-E009-071
URI: http://hdl.handle.net/11536/100636
https://www.grb.gov.tw/search/planDetail?id=2183386&docId=349739
顯示於類別:研究計畫