標題: | 應用於先進邏輯與節能電子電路之先進非對稱金氧半場效電晶體技術(I) Development of Advanced Asymmetrical MOSFETs for High-Performance Logic and Green Electronics Applications(I) |
作者: | 黃調元 HUANG TIAO-YUAN 國立交通大學電子工程學系及電子研究所 |
關鍵字: | I-line雙重微影技術;非對稱源汲極接面濃度;斜角度離子佈植;非對稱大傾角佈植 |
公開日期: | 2010 |
摘要: | 本計劃將研究多種前瞻且富潛力的具有非對稱源/汲極結構的金氧半場效電晶體。為達研究的目的,首先我們將發展一種I-line雙重微影技術,用以形成線寬小於100奈米的元件結構,並搭配獨立源極/汲極接面設計與製作,研製與開發多種奈米級非對稱結構的場效電晶體。非對稱的結構不僅突顯雙重微影技術的優點,而且藉由調變不同源極/汲極接面的製程參數,是最佳化電晶體特性與可靠度的一良好途徑。另一方面,由於積體電路晶片功率消耗可觀的耗電量,是造成嚴重能源短缺的主因之一。微電子產業對“綠色”技術需求的迫切性不言可喻。為了實現在室溫下讓次臨界擺幅小於理想值60mV/dec的目的,非對稱結構的特殊應用:穿隧式場效電晶體及相關改良結構等概念已被提出。由於可有效降低操作電壓與功率耗損,此元件被視為是深具潛力的一項技術,也成為學習如何解決當下能源短缺的重要良策。本計劃也將嘗試發展運用邊襯式奈米線通道結構、垂直通道、異質矽鍺、全包覆式閘極等結構於穿隧式場效電晶體之技術,以期增加穿隧機率與提升導通電流。 This project plans to investigate a number of novel and potential MOSFETs featuring asymmetrical source/drain. An ingenious I-line double-patterning technique capable of generating sub-100 nm gate patterns is proposed in this project to facilitate the fabrication of various nano-scale asymmetric devices in which the source and drain can be designed and processed independently. Asymmetric structures actually stand out the pros of double patterning lithography technique. It also provides a useful gateway to the optimization of device characteristics and reliability by means of modulating different process parameters for forming the source/drain junctions. On the other hand, the appreciable power consumption consumed by IC chips is one of the culprits for globe energy crisis. Development of a “green” device technology which can dramatically cut down the power consumption during operation is thus an urgent need. For realizing subthreshold swing smaller than the limit of 60 mV/dec at room temperature, tunneling field-effective transistor (TFET), an inherent asymmetrical device, is feasible. With its effectiveness in reducing the operation voltage and therefore the power consumption, such type of green devices is regarded a useful successor to modern CMOS technology. This project also intends to implement several advanced structures, including nano-wire spacer, vertical channel, SiGe hetero-structure, and gate-all-around configuration, into the fabrication of the TFETs, aiming at increasing the tunneling probability and boosting the drive current. |
官方說明文件#: | NSC99-2221-E009-172 |
URI: | http://hdl.handle.net/11536/100709 https://www.grb.gov.tw/search/planDetail?id=2113383&docId=337736 |
顯示於類別: | 研究計畫 |