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dc.contributor.author張翼en_US
dc.contributor.authorCHANG EDWARD YIen_US
dc.date.accessioned2014-12-13T10:46:53Z-
dc.date.available2014-12-13T10:46:53Z-
dc.date.issued2009en_US
dc.identifier.govdocNSC97-2221-E009-156-MY2zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/100901-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1760373&docId=300560en_US
dc.description.abstract過去四十年元件線寬的微縮一直是Si 半導體提升元件特性最直接也最有效的方 法,但是最近幾年碰到了幾個難以克服的問題。而這些問題難以解決的原因在於矽半導 體本身材料特性的限制。因此導入新的高載子遷移率材料,如砷化鎵等三五族半導體, 被視為下一個世代提升元件特性最有效的方法之一。矽電晶體之物理閘極線寬目前為90 奈米,下一階段約為50 奈米世代,預計於2011 年,電晶體的尺度約為10 奈米,已經 接近半導體製程上的物理極限。在此線寬下使用具有較高電子遷移率特性的三五族材料 被視為延伸莫爾定律的解決方案之一。 本計畫的主要目的是製作電流截止頻率(fT)高於500GHz 的電晶體,將使用閘極線 寬為40 奈米與超高電子遷移率的砷化銦(InAs)為通道材料。評估其操作在超高頻率時, 應用於超低消耗功率、高速邏輯電晶體之可行性。砷化銦材料的優點在於電子在此材料 內移動時有極高的電子遷移率,而且在較低電壓時就可以獲得相當大的驅動電流。因此 只要使用砷化銦為通道層材料,就可以有效提高電子遷移率以及電子浮移速度,使得元 件操作更快速更高頻而且具有更好的特性。此外還可以使元件在較低電壓下操作,將可 以大幅降低電晶體的消耗功率,達到超低電壓、超低功率的操作需求。此外,將配合本 實驗室砷化鎵完整的製程線,可製作出操作在超高頻率、超低電壓之數位邏輯積體電路。zh_TW
dc.description.abstractScaling device dimensions has been the most powerful and effective strategy to boost device performance for the last 40 years. However, a number of obstacles have failed the effectiveness of this strategy. Unfortunately, some of the obstacles seem to be insurmountable by using the traditional “silicon technology approach”. Therefore, introducing the materials, such as GaAs III-V based semiconductors, is almost inevitable for the enhancing device performance. The physical gate length of Si transistors used in current 90 nm generation node is about 50 nm. The size of transistor will reach 10 nm in 2011 which is almost the limit of process technology. In order to extend Moore’s law well into next decade, Using higher speed III-V semiconductor compound materials in the device structure is one of the promising solutions for the CMOS technology. The goal of this work is to fabricate an ultra-high speed device with an over fT 500 GHz of current gain cutoff frequency (fT) using InAs-channel layer and 40-nm gate length. In general, the high electron mobility and high electron drift velocity can be obtained at a lower applied voltage with using InAs-channel due to the low energy bandgap. The power consumption can be reduced effectively using InAs-channel devices. Furthermore, our group has the first one full III-V based foundry line in the academic area. To integrate the IC process technology with the 500 GHz device, an ultra high speed, ultra low power logic IC can be fabricated in this work.en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.subject砷化銦zh_TW
dc.subject高電子遷移率zh_TW
dc.subject超低功率操作zh_TW
dc.subject500 GHzzh_TW
dc.subjectInAsen_US
dc.subjectHEMTen_US
dc.subjectHigh frequencyen_US
dc.subjectLow poweren_US
dc.subject500 GHzen_US
dc.title電流截止頻率大於500GHz之砷化銦通道高電子遷移率電晶體其製作與高速邏輯應用之評估zh_TW
dc.titleFabrication and Evaluation of Ft .gt. 500 GHz InAs-Channel HEMTS for High Speed Logic Applicationsen_US
dc.typePlanen_US
dc.contributor.department國立交通大學材料科學與工程學系(所)zh_TW
顯示於類別:研究計畫