标题: | ㄧ个全新的晶片-封装-印刷电路板共同设计与共同最佳化方法 A Novel Methodology in Chip-Package-Board Co-Design and Co-Optimization |
作者: | 陈宏明 Chen Hung-Ming 国立交通大学电子工程学系及电子研究所 |
关键字: | 晶片—封装—印刷电路板共同设计;覆晶封装;Chip-Package-Board Codesign;Flip-Chip |
公开日期: | 2009 |
摘要: | 因为现今的产品中SoC 与SiP 的设计需求有遽增的趋势,因而快速的提高了晶片、封装 与印刷电路板(PCB)的设计困难度。为了应付更多數量的输出入接脚(I/O pin)、更高速的讯号 以及更密集的晶片密度等问题,IC 设计工程师常使用覆晶封装(flip-chip package)的方式來取 代一般打线封装(wire-bond package)设计。然而,传统的覆晶封装—印刷电路板共同设计 (package-board codesign)以手动方式安排接脚位置,不但耗时、效率低而且必须完全仰赖工 程师的经验。本计划即提出一个可以自动安排封装接脚位置与最佳化封装尺寸的设计流程。 此计划共分成三个部份:首先,我们将建立一组可以同时考虑讯号完整性(Signal integrity)、电源供应(Power delivery)与可绕线率(Routability)的讯号—接脚样板(Signal-pin pattern),利用这些样板建构讯号—接脚区块(Signal-pin block),最后再以一区块摆置演算法 (Block floorplanning algorithm)完成最后的接脚位置图并且达到最小的封装尺寸。第二部份, 我们将试着应用IC 内部区块摆置(Floorplanning)的方法來安排讯号—接脚区块已达到晶片效 能与成本的最佳化,例如使用‘范围限制(Range constraint)’与‘模拟退火技术(Simulated annealing technique)’。最后,我们会建立一组IC、封装与印刷电路板模型(Model),并且提 出一个完整的晶片—封装—印刷电路板共同设计流程(Chip-package-board codesign flow),在 此设计流程中得以共同模拟(Co-simulation)与共同最佳化(Co-optimization)。 Due to the trend of more and more SoC and SiP projects, the complication in package designs and signal interaction between package and board is increasing very rapidly. Since the typical peripheral wire-bond design may not be appropriate for some particular designs, flip-chip package becomes a better choice. In conventional flip-chip package-board codesign, engineers designate the pin-out manually, which is very time-consuming and always postpones the time-to-market (TTM) of products. This project will propose a method of automatically generating the BGA pin-out by pin-block design and floorplanning, thus speed up the developing time dramatically. The project contains three parts (for three years): first, we propose the signal-pin patterns for pin-block construction in package design. Signal integrity, power delivery, and routability will be accounted for in those patterns. This helps to speed up the process of pin-out designation. And then we propose a near optimal approach to minimizing package size by mathematical programming formulation. Second, we will try to develop a novel planning algorithm by using a new representation for pin-block placement and defining range constraints in simulated annealing technique to optimize the location of pin-blocks. Finally, we will establish the chip-package-board codesign flow and create package-interconnection models. Then chip and package are co-simulated and co-optimized. |
官方说明文件#: | NSC97-2221-E009-174-MY3 |
URI: | http://hdl.handle.net/11536/101130 https://www.grb.gov.tw/search/planDetail?id=1752405&docId=298742 |
显示于类别: | Research Plans |
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