適用於使用開路放大器設計之低功率管線式類比數位轉換器的數位校正方法

Abstract

隨著CMOS 製程不斷的進步，電晶體的通道越來越小，因而使得電晶體之間的特性差 異度越來越大。以65nm 製程為例，電晶體通道內的原子數只有數百個之譜。任何原子 排列的差異，將嚴重影響元件的匹配度，造成電路特性與模擬的極大差異。也因此， 各式可製造性設計(design-for-manufacturing)技術近來成為數位電路設計的重要研究課 題。 對於類比電路設計而言，使用先進製程設計的難度更是大為增加。首先，電晶體的短 通道效應造成其本質增益(intrinsic gain) 降低至10 左右。另外，為了維持可靠度，先 進製程的供應電壓已降至一伏特以下，許多傳統的設計技巧如堆疊結構(cascade configuration)已不再適用。而元件電氣特性的大幅漂移，更是類比電路設計工程師的夢 靨。舉例而言，如何保證電流鏡(current mirror)的輸出入電流比值不會因電晶體的電氣 特性的大幅漂移而改變幾乎是不可能的事。因此，我們需要發展出新的設計方法以克 服種種問題。 類比數位轉換器為大多數系統的基礎構成電路之一。而管線式類比數位轉換器為眾多 架構之中相當受歡迎的一種，它具備有低耗能、可提供中高速取樣率、與中高解析度 的能力。然而，即便是使用如0.35um 等舊製程，管線式類比數位轉換器的解析度仍受 限於電路元件的匹配度，很難超過10 位元。 使用數位校正方法來設計管線式類比數位轉換器是一種可行的方案 其觀念是不論元 件特性如何飄移，若我們可以在不影響電路正常工作的情形下以數位方式測量得製作 出的電路特性與預期的不同處，那我們就可以利用數位方法將元件特性漂移所造成的 誤差從輸出減去，最後便能得到正確的結果。換言之，藉由加入少許數位校正電路， 我們不再需要高效能且高耗能的類比電路，因此可以簡化類比電路設計。此外，如果 該數位校正方法可以同時校正線性與非線性誤差，那麼我們可以更進一步使用開路放 大器取代傳統使用負回授的電路來設計管線式類比數位轉換器，以獲得低功耗、高頻 寬、與小面積的優點。此種數位校正方法特別適用於先進製程，因為先進製程的數位 電路更小、更便宜、且更快速。 因此，本計畫所要提出的是發展出一種適用於使用開路放大器管線式類比數位轉換器 的數位校正方法，藉由此方法來實現低功率、低晶片成本、高解析度、與高取樣率的 管線式類比數位轉換器。計畫目標分為三年： 在第一年中我們將發展出適用於使用開路放大器之管線式類比數位轉換器的數位校正 方法，並藉由行為模型驗證。我們的目標在於解決已知數位校正方法的缺點例如過於 複雜或對輸入訊號有不切實際的假設等，並且可以在背景(background)執行校正的數 位校正方法。 在第二年內，我們將以0.18μm 的製程技術進行類比及數位電路設計，並完成電路佈 局，實現一個12-bits，200-MS/s，150mW 的開迴路導管式類比數位轉換器，且完成 晶片量測。我們也將藉由測試結果，分析電路行為是否與理論相符。 基於第二年的設計經驗與分析結果，我們將在第三年內以90nm 的製程技術實現一個 可操作在500-MS/s，具12-bits 解析度，僅耗100mW 的開迴路導管式類比數位轉換器， 並完成量測驗證。 基於我們在類比數位轉換器的設計與測試的經驗，我們有信心可以順利完成本計畫。

As CMOS technology keeps shrinking down, the channel length of the MOSFET is so small such that there are only hundreds of atoms in it. Consequently, any subtle difference between two MOSFETs’ channels will make their electrical characteristics, such as the threshold voltage, severely diverse. That’s the reason why the design-for-manufaturability (DFM) technique becomes an important issue for the digital circuit design using deep sub-micron CMOS processes. For analog circuit designers, their situations are even worse than the digital guys. First, the short-channel effect limits the intrinsic gain of a deep sub-micron MOSFET down to only ten or around. This makes designing a high gain amplifier very difficult in a conventional way. In addition, the supply voltage currently is down to 1V for a 90 nm process to avoid reliability issue. Under such a low supply voltage, many traditional analog circuit design techniques such as cascoding are no longer applicable. The huge deviation of the electrical characteristics of MOSFETs is the most horrible nightmare for analog designers. Just image that the current ratio of a basic current mirror now becomes unpredictable even the MOSFETs are placed very close to each other. How can we design the circuits which are much complex than the current mirror? Therefore, we have to figure out some novel design methods to address these issues in deep sub-micron analog circuit design. An ADC is a basic building block for most mixed-signal systems and the pipelined ADC is a very popular ADC architecture. It is suitable for the application requiring a sampling rate around several tens MHz and a resolution around 8 to 10 bits. However, the pipeline ADC is hard to achieve a resolution as high as 12 bits even using an old process such as 0.35um. It is the mismatch of the devices that limits the resolution of the ADC. The digital calibration scheme is a promising approach for advanced ADC design. The idea is that if we can digitally estimate the characteristics of the practical circuits without interrupting their normal operations, then we are able to calculate the errors that the ADC’s outputs have. By subtracting the digitized error from the digital output, we can have the correct digital outputs. That is, we don’t need high performance analog block any more thanks to the additional digital calibration circuits. It leads to another interesting scenario: if the digital calibration scheme can calibrate both the linear and non-linear errors, we can replace the original feedback amplifiers in the pipelined ADC with the open-loop ones. The open-loop amplifier achieves lower power, small area, and wider bandwidth than the closed-loop one. Similar to the case of advanced MOSFETs, the major issue of using open-loop amplifiers is the huge deviation of their electrical characteristics. Of course, this is not an issue by applying the digital calibration scheme. In addition, digital calibration schemes are more suitable in advanced technology since its major hardware overhead is digital and each MOSFET in the digital circuits becomes cheaper, smaller, and fasters when its channel length is getting shorter. This project proposes to develop a digital calibration scheme for pipelined ADCs. With the new digital calibration scheme, we will realize low power, low cost, high resolution, and high sampling rate pipelined ADCs. The project goals in the following 3 years are: In the first year, we will develop a digital calibration scheme and verify the scheme by behavioral simulations. The target is to develop the digital calibration scheme that can calibrate the pipelined ADC with open-loop amplifiers, while it does not suffer from the known issues of the state-of-the-art works such as being too complex to implement and some unrealistic assumptions on the input signal. In the second year, we will realize a 12-bits, 200MS/s, 150mW pipelined ADC with open-loop amplifiers using a 0.18um CMOS technology. The test chip will be analyzed to find out the difference between practice and theory. Base on the results of the second year, we will improve our design and realize a 500MS/s, 12-bit, 100mW pipelined ADC using a 90nm CMOS process. Based on our experiences in ADC testing and design, we believe we can meet the project goals on time.