完整後設資料紀錄
DC 欄位語言
dc.contributor.authorHuang, Hong-Weien_US
dc.contributor.authorChen, Ke-Horngen_US
dc.contributor.authorKuo, Sy-Yenen_US
dc.date.accessioned2014-12-08T15:13:10Z-
dc.date.available2014-12-08T15:13:10Z-
dc.date.issued2007-11-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2007.907175en_US
dc.identifier.urihttp://hdl.handle.net/11536/10158-
dc.description.abstractThis paper proposes temperature-independent load sensor (LS), optimum width controller (OWC), optimum dead-time controller (ODC), and tri-mode operation to achieve high efficiency over an ultra-wide-load range. Higher power efficiency and wider loading current range require rethinking the control method for DC-DC converters.. Therefore, a highly efficient tri-mode DC-DC converter is invented in this paper for system-on-chip (SoC) applications, which is switched to sleeping mode at very light load condition or to high-speed mode at heavy load condition. The efficiency improvement is upgraded by inserting new proposed dithering skip modulation (DSM) between conventional pulse-width modulation (PWM) and pulse-frequency modulation (PFM). In other words, an efficiency-improving DSM operation raises the efficiency drop because of transition from PWM to PFM. Importantly, DSM mode can dynamically skip the number of gate driving pulses, which is inverse proportional to load current. Simplistically and qualitatively stated, the novel load sensor automatically selects optimum modulation method and power MOSFET width to achieve high efficiency over a wide load range. Moreover, optimum power MOSFET turn-on and turn-off delays in synchronous rectifiers and reduced ground bounce can save much switching loss by current-mode dead-time controller. Experimental results show the tri-mode operation can have high efficiency about 90% over a wide load current range from 3 to 500 mA. Owing to the effective mitigation of the switching loss contributed by optimum power MOSFET width and reduction of conduction loss contributed by optimum dead-times, the novel width and dead-time controllers achieve high efficiency about 95% at heavy load condition and maintain the highly efficient performance to very light load current about 0.1 mA.en_US
dc.language.isoen_USen_US
dc.subjectDC-DC converteren_US
dc.subjectdelay-line chainen_US
dc.subjectdithering skip modulationen_US
dc.subjectground bounceen_US
dc.subjectload sensing circuiten_US
dc.subjectoptimum dead-timeen_US
dc.subjectwidth controlleren_US
dc.titleDithering skip modulation, width and dead time controllers in highly efficient DC-DC converters for system-on-chip applicationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2007.907175en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume42en_US
dc.citation.issue11en_US
dc.citation.spage2451en_US
dc.citation.epage2465en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000250524500015-
dc.citation.woscount56-
顯示於類別:期刊論文


文件中的檔案:

  1. 000250524500015.pdf

若為 zip 檔案,請下載檔案解壓縮後,用瀏覽器開啟資料夾中的 index.html 瀏覽全文。