奈米級混合信號式電路技術---子計畫四：奈米級CMOS製程之積體電路靜電放電防護技術

Full metadata record

DC Field	Value	Language
dc.contributor.author	柯明道	en_US
dc.contributor.author	KER MING-DOU	en_US
dc.date.accessioned	2014-12-13T10:49:44Z	-
dc.date.available	2014-12-13T10:49:44Z	-
dc.date.issued	2009	en_US
dc.identifier.govdoc	NSC98-2221-E009-113-MY2	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/101773	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=1906194&docId=315956	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	奈米級混合信號式電路技術---子計畫四：奈米級CMOS製程之積體電路靜電放電防護技術	zh_TW
dc.title	ESD Protection Techniques for Nanoscale CMOS Integrated Circuits	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電子工程學系及電子研究所	zh_TW
Appears in Collections:	Research Plans