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dc.contributor.author單智君en_US
dc.contributor.authorSHANN JEAN JYH-JIUNen_US
dc.date.accessioned2014-12-13T10:50:20Z-
dc.date.available2014-12-13T10:50:20Z-
dc.date.issued2008en_US
dc.identifier.govdocNSC95-2221-E009-065-MY3zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/102063-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1582256&docId=271014en_US
dc.description.abstract計算機的發展,隨著使用者需求的增加與各種應用的多元化,使得設計上越趨複
雜,晶片內單位面積的電晶體數量也因此快速增加。近年來,不論從散熱問題面或可攜
式產品的需求面來看,低功率技術的開發均為重要的產業發展方向。本計畫擬以三年為
期,由計算機架構的角度出發,探討相關的低功率設計技術。
本計畫提案的研究內容將以低功率、低耗能且兼顧效能為目的,依動態分支預測、
匯流排系統、及快取記憶體等三大方向規劃各研究課題,概述如下:
.. 動態分支預測方面:著重於消除無意義的動態分支預測器之存取、分支標的緩衝器
(Branch Target Buffer, BTB)之動態電源管理技術、以及BTB 與快取記憶體
(Instruction Cache)之整合低功率技術等相關議題。
.. 匯流排系統方面:著重於各類位址、指令、及資料在 Full-width Bus 與Narrow Bus
上的編碼技術開發。
.. 快取記憶體方面:著重於迴圈緩衝器(Loop Buffer)之低耗能設計以及L1 Cache 與
L2 Cache 之動態電源管理技術。
本研究計劃符合國科會資訊學門之「前瞻性系統單晶片架構」重點規劃主題中的「低
耗能設計」研究課題,為目前產學研究的重要發展趨勢。基於本研究團隊對計算機架構
及低功率技術的既有研究基礎,期望能將之應用於開發上述低耗能關鍵技術,以對我國
低功率計算機技術的設計開發能力及經濟利益有所助益,並培育相關領域所需之人才。
zh_TW
dc.description.abstractAs the demand for a computer』s performance and its versatility being ever increasing, its
design is becoming very complex. The amount of circuits, within a chip or a system, is also
sky rocking. On the other hand, in recent years, high demands for both lowered heat
dissipation cost and product portability make development of low-power techniques an
eye-catching direction. This proposal bases on the computer architecture and explores the
important low-power design techniques, in a three-year research effort.
The objective of this research project is to explore low-power, low-energy design
techniques without sacrificing too much performance. We categorize such techniques into
three domains: Dynamic branch prediction, the bus system, and cache memories. Each of
these domains contains a number of research topics, as described below:
.. Domain1: Dynamic branch prediction-Topics include Elimination of unneeded
dynamic branch predictor accesses, Dynamic power management for BTB (branch target
buffer), and Integrated design of BTB and instruction cache.
.. Domain2: The bus system-Topics include bus information encoding techniques for
assorted address/instruction/data/multiplexed busses with full width or narrower.
.. Cache memories-Topics include Loop buffer design, and dynamic power management
for L1/L2 caches.
Contents of this proposal comply with key promotional research topic 「Advanced
System-on-A-Chip Architecture - Low-Power Designs」 as outlined by the Information
Engineering Discipline, Engineering Division, National Science Council. This is a vital
research direction for industry as well as academic and research institutions. Based on our
research expertise in computer architecture and low-power technology, we propose to extend
our work to develop those low-power key techniques listed above. It is expected that upon the
completion of this research, our domestic capacity in low-power computer designs and
industrial revenues will be greatly upgraded. Its execution also will certainly produce a
good number of urged quality researchers in digital design and SoC development.
en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.subject低功率zh_TW
dc.subject計算機zh_TW
dc.subject動態分支預測zh_TW
dc.subject匯流排zh_TW
dc.subject快取記憶體zh_TW
dc.subjectLow-poweren_US
dc.subjectComputeren_US
dc.subjectDynamic branch predictionen_US
dc.subjectBusen_US
dc.subjectCache memory.en_US
dc.title低功率計算機設計zh_TW
dc.titleLow-Power Computer Designen_US
dc.typePlanen_US
dc.contributor.department國立交通大學資訊工程學系(所)zh_TW
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