可攜式EEG/EKG/fNIRS腦神經影像系統研發暨其整合型生醫感測處理晶片系統設計---子計畫三：低功耗生醫信號處理及影像重建系統單晶片設計(I)

Abstract

本計畫在設計一顆低功率生醫訊號處理及影像重建系統單晶片(SoC)，應用在可攜式的腦神經影像儀之核心硬體。此晶片系統架構主體為一個新穎的二維獨立成份分析(2D-ICA)影像處理器並結合資訊壓縮模組以及短距通訊模組。此系統單晶片收集來自前端偵測模組的生醫訊號其中包含了fNIRS、EEG及EKG的訊號，並進行即時的生醫訊號處理及影像重建運算，將處理完的結果送至後端的science station。此系統單晶片進行影像重建功能時，除了自身取得的影像資訊，另外必須從其周圍四顆fNIR node擷取raw image data，以進行五組的2D-ICA影像去雜訊及重建演算。當即時解析所擷取含雜訊的影像資訊時，必須並配合ARM micro computer控制EKG信號，以便補償血液流動與血管擴張時對fNIR image所產生的雜訊。經過獨立成份分析影像處理後的清晰fNIR影像資訊會採JPEG無失真壓縮機制，保存完整醫學影像資訊，最後以無線網路(WLAN)傳輸至science station進行3D影像重建。 我們提出一個由2×2 node 組成的cluster架構，此種擺放方式可以使得整體node 陣列所需的擺放面積大幅減少，單位node面積減少一半，還可以提升受測者的舒適度；此外我們引進super node concept，將所有cluster內所有node raw image在2D-ICA演算完畢後都由ARM 7控制，傳輸至cluster內同一顆super node，並批次傳輸至science station，達到降低功率耗損，增加頻寬使用的效率。 本子計畫的目的便是針對總計劃輕量化可攜式即時fNIR影像去雜訊的需求，來設計製作『低功率生醫訊號處理及影像重建系統單晶片』，單晶片系統包含ICA image pre-processor、2D-ICA image processor、power management module以及ARM IP，為了節省功率消耗，我們未來將採用90m製程規格晶片下線。研究人員將根據以下三點來建構系統：（1）設計fNIR影像處理器（2）設計cluster內node communication、super node低功率，高頻寬使用效率ARM IP。（3）結合EKG及node自身與周圍raw image資訊，找出最佳fNIR/EKG演算法整合至影像重建系統單晶片中。SoC系統驗證將採用CIC-concord平台並與CIC合作開發適合此計畫使用，並將所有子系統模組IP化並整合至此平台。 第一年計畫摘要： 本計劃將發展2D-ICA演算法並據之來設計功能性近紅外線 (fNIR)影像處理晶片。此晶片將處理來自子計畫2 經過ADC傳送過來的多樣生醫訊號。本計劃初期演算法設計冀求能達成即時處理生醫影像訊號的功能，另考慮晶片設計需達到低功率消耗之要求，故此設計也需精簡的fNIR影像處理演算法。為了達成可攜式fNIR影像處理系統，本計劃將研發低功耗cell based libray，並以之來設計低功率的影像處理晶片。研究初期將以FPGA驗證根據2D-ICA演算法發展出來之硬體雛型規格；另一方面，本計劃也將發展JPEG無失真壓縮演算法，並以FPGA平台來驗證根據無失真JPEG演算法發展出來之硬體雛型規格。在此階段，本計劃將協助建立對應於子計畫1所需之生物規格與驗證方法。 第二年計畫摘要： 第二年的工作預計採用TSMC 0.13um 1P6M mixed-signal 製程，以晶片實現第一年經FPGA發展出來之演算法硬體雛型。此外，本系統亦整合ARM IP，設計系統pipeline流程以及communication控制器。本年度將持續完成系統與science station的wireless communication，以System in Package (SiP)方式完成fNIR/EEG生醫信號處理平台。最後，評估系統穩定性及容錯度是否符合當初制定的規格。 第三年計畫摘要： 根據子計畫1提供之相關於fNIR與全域EKG （global EKG）訊號時變關係規格，近一步研發整合EKG訊號至fNIR image processor，以改良fNIR/EKG影像成像效果。第三年的工作將採用UMC 90nm mixed-signal製程來整合fNIR image processor以及wireless communication module，冀期完成整合多功能fNIR/EEG/EKG 單晶片系統，此單晶片測試及驗證將使用CIC-concord平台來實踐。本計劃將與子計畫1配合來完成系統層次的整合，並協助進行fNIR/EEG/EKG生醫訊號科學分析及應用。

In this project, we propose a biomedical signal processing and image reconstruction SoC (System on a Chip) design with a low power consumption architecture. The novel 2 dimensional independent component analysis (ICA) image processor can merge raw image data acquired from neighbor image sensors as well as its own image, and string out a clear fNIR node image that has been removed biological noise. Since the functional NIR recordings are naturally highly correlated with the cardiac rhythm, the signal that removes these bias signals introduced by the cardiac rhythm can be controlled by an ARM micro controller. In order to preserve the original medical image that will be investigated by professionals later, we implement the lossless JPEG compression algorithm on the SoC. The compressed medical image will be sent to the science station for further 3D head image reconstruction. A cluster that contains 2×2 nodes architecture is presented in this project. Such node arrangement can dramatically reduce node array spacing, and so does the unit node size. The patients will also experience a better medical treatment while taking fNIR/EEG examination. We introduce a super node concept in our design, with which all nodes clear image that have been processed by the 2D-ICA image processor will pipeline sending to the science station through a specific super node. A low power consumption with high bandwidth utility goal will be reached under the architecture. Abstract of 1st year project: Due to the requirement of real time processing medical image, we will first design an image preprocessor for 2D-ICA image processing stage. The key point of design mythology will focus on degrading the whole complexity of the algorithm and low power consumption. The proposed system utilizes a fully custom circuit library for low-power consumption design so that we can reach the portable system goal. We will validate the algorithm of 2D-ICA in FPGA. Beside, we also integrate the lossless JPEG algorithm to compress the ICA output clear image. Abstract of 2nd year project: We will use TSMC 0.13um 1P6M mixed-signal process to implement our fNIR/EKG chip prototype, which has been developed and validated in FPGA. Besides, the prototype will integrate ARM IP to control the architecture pipeline flow and communication. In this year, we will use System in Package (SiP) technique to develop our fNIR/EEG biomedical signal processing platform and assess the platform stability and then compare it with our proposed specification. Abstract of 3rd year project: To have better fNIR/EKG image reconstruction result, we will integrate EKG signal that is provided from sub-project 1 into fNIR image processor. UMC 90nm mixed-signal process are used to implement our low power fNIR/EEG/EKG SoC, which has combine fNIR image processor and wireless communication module. We will use CIC-concord to test and validate SoC. Eventually, the proposed sub-project will assist sub-project 1 to finish system level integration and therefore execute fNIR/EEG/EKG biomedical signal analysis and application.