後次微米時代新興電子設計自動化技術之研究---子計畫一：符合次世代晶片上通訊思維之具備幾何考量的系統架構合成技術(I)

Abstract

隨著製程的進步，單一元件(device)逐年縮小化，使得單一晶片(chip)可整合更多之電晶體數目及功能模組(modules)，同時，也使得單一元件的切換速度愈來愈快，進而可提高系統的操作頻率。然而，在系統中無可避免地會需要模組間的資料交換，這些通訊行為在晶片上代表著模組間需要長導線相互連接。相對於單一元件可由製程的進步得到切換速度的提昇，這些晶片上的長導線反而因為元件的縮小化而導致傳輸速度的惡化。在未來35奈米的製程中，訊號在橫跨晶片之長導線上之延遲時間將會是系統運作之時脈週期的十數到數十倍之譜。由於元件的縮小化是必要的趨勢，而現有之大部份設計自動化軟體及設計方法並無力處理未來長導線將會帶來之多時脈週期(multi-cycle)通訊的問題。因此，業界將會需要革命性的設計方法及思維作為因應。 由於系統上各模組間通訊所需要之通訊時間決定於佈局(floorplaning)和擺放(placement)之後的結果，而在已知文獻及我們的分析中發現，各模組間的通訊時間對系統效能之影響甚巨，因此在晶片設計前期已不能不將佈局及擺放同時考慮進去。本計畫將探討分散式暫存器架構(distributed register architecture)，在考慮多時脈週期通訊的情形下，研發高階合成(high level synthesis)之設計自動化軟體，在同時考量排程(scheduling)、模組的配置(allocation and binding)、佈局和擺放、繞線(routing)及系統效能的情形下，從高階設計語言自動合成出暫存器傳送層級(register transfer level)硬體設計語言(hardware deign language)。

As the technology keeps advancing, the device is miniaturized year by year. The miniaturization makes more transistors and more modules being integrated into one single chip. It also makes the switching of the transistors faster and faster, and hence increases the system operating frequency. However, data transactions between modules in a system are unavoidable, and these transactions require physical long wires for interconnection. In contrast to the benefits transistors can get due to the advancing technology, the signal propagation delay on long wires is getting worse. In 35nm technology node, the propagation delay on a cross-chip long wire can be dozens of the clock cycles. Since the trend of miniaturization is mandatory and most current EDA tools cannot handle the multi-cycle communication issue due to the long wires, the industry definitely needs a revolutionary design methodology to overcome the problem caused by long wires in the future chips. According to the up-to-date literature and our analysis, the communication latency among modules in a system greatly impacts the system performance. However, the exact communication latency is not available until the system is floorplanned and placed. Hence floorplanning and placement must be taken into consideration in the early stage of chip design as well. In this project, we will develop an automation tool for distributed register architecture (DRA) by considering the multi-cycle communication paradigm. Designs of chips written in high level design language will be synthesized automatically to a register transfer level version by taking scheduling, resource allocation/binding, Floorplanning/placement, routing and system performance into consideration simultaneously.