後次微米時代新興電子設計自動化技術之研究---子計畫五：考慮可製造化、可靠度與良率的繞線系統(I)

Abstract

隨著晶片製造技術進入了深次微米時代，在製造過程當中的物理效應變得越 來越重要。舉例來說，為了讓金屬層密度平均使得化學機械磨光程序後的氧化物 厚度平均而須要在布局之後加入虛擬填充金屬。但是隨著線寬越來越窄，在布局 完成之後所插入的虛擬填充金屬影響導線的耦合電容效應也會越來越高。此外， 隨著線寬以及空間越來越小，隨機缺陷發生的機率也越來越高，因此隨機缺陷也 變成了一個良率下降的重要因素。此外電子飄移效應也因大電流通過導線而可能 使得導線最後會變成斷路。在此子計畫當中，我們打算設計一個考慮化學機械磨 光的繞線系統，以及良率導向的非點格式繞線器以及考慮電子飄移效應的繞線器 以處理製程當中的物理效應。 儘管我們可以透過在佈局之後的虛擬金屬填充來控制局部密度，以減少在化學機 械磨光之後氧化物以及金屬厚度的影響，虛擬金屬填充仍然有其限制，虛擬金屬 填充無法使金屬密度達到完全平均的分佈。所以我們渴望在繞線的階段將金屬密 度考慮進去。在第一年，我們計畫發展一個考慮化學機械磨光的繞線系統，其中 包含了一個化學機械磨光導向的廣域繞線器，以及一個化學機械磨光導向的細部 繞線器。 隨機缺陷的發生主要是因為兩種缺陷：未連接以及短路缺陷。當我們從鋁製程轉 換到銅製程，未連接缺陷發生的狀況比短路缺陷要更多。隨機缺陷通常存在於鄰 近的導線之間，或是存在於導線自己本身。所以繞線階段是一個很理想的階段來 考慮隨機缺陷。在第二年，我們會研究隨機缺陷模型並且讓我們的細部繞線器可 以處理隨機缺陷。並且，我們也會發展一個在繞線之後的最佳化工具，以解決更 多隨機缺陷的問題。 電子飄移是由於導線上有過高的電流所造成，在次微米的IC 設計裡，信號傳輸 線與電源線上因高密度電流所引起的電飄移現象相當常見，且在考量良率與可靠 度上電子飄移現象的問題是越來越受到重視，尤其當製程尺寸越微小，電子飄移 所造成的傷害就越顯著，因此如何在實體設計時能越早開始考量電飄移現象藉此 提高良率與可靠度就顯得更加重要。在這份計畫書內我們首先會簡介電子飄移現 象所造成的問題，以及電子飄移現象跟電流密度與溫度之間的關係，接著簡介實 體設計的方式來影響電子飄移現象，最後提出一個在繞線時考量電子飄移現象的 方法來進一步改善良率與可靠度。

With the arrival of deep-submicron era, the physical effect during manufacturing process becomes has a deep impact on the manufacture yield. For example, the inserted dummy fills for averaging metal density to even the oxide surface after chemical mechanical polishing (CMP) process increase the coupling capacitance of a wire. Meanwhile, as wire width and space continue to shrink, the probability of the occurrence of random defect grows, where a random defect probably causes a short-wire or open-wire failure. Thus the random defect also becomes an important factor to decrease manufacture yield. Furthermore, electromigration is a serious problem concerned with the circuit reliability. Electromigration often occurs in the slim part of a wire conducting with mass current, and the wire finally becomes open in the slim part. In this subproject, we plan to design a CMP-aware routing system, a random-defect-aware router and an electromigration-aware router to deal with the physical effect in the manufacturing process. Recent researches have shown to successfully reduce the thickness of oxide and metal after CMP process by inserting dummy fills at the post-layout stage to control the local density, dummy fills insertion at the post-layout stage still has its limitation since dummy fills can not uniformly distribute metal density. Thus it is desired to consider the metal density problem in the early design stage, such as routing stage. We plan to develop a CMP-aware routing system in the first year, which contains a CMP-aware global router and a CMP-aware detailed router. The random defects mainly result in two types of defects: wire open and wire short. While aluminum replaces copper as the material of metal interconnections, open defects dominate over short defects. The random defects often occur either between physically adjacent interconnections or on single interconnection. Hence, it is an ideal stage to take random defects into account in the routing stage. In the second year, we will survey random defect models and augment our detailed router to deal with random defects. Also, we will develop a post-routing optimizer to further solve the random defects problem. The electromigration effect within current-density-stressed signal and power lines is a ubiquitous and increasingly important reliability and design problem in sub-micron IC design. Electromigration is caused by excessive current density stress in interconnect. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, therefore it is essential to consider it for reliability issue as early as possible during physical design stage. In this proposal, we first introduce the electromigration problem and its relationship with current density and temperature. We then present some physical design methods that consider electromigration. In this year, we plan to develop an electromigration-aware routing method to further improve the yield and reliability.