使用60GHz之室內十億級位元傳輸率之無線基頻傳收機---子計畫二：適用於十億級位元傳輸率無線個人區域網路應用之異質多處理器核心系統晶片平台(I)

Abstract

2007 年新制訂的IEEE 802.15.3c 標準（WPAN），屬於短程（約10m） 寬頻無線通訊系統，使人們在室內的活動不再受限於傳輸線。802.15.3c 系統 可提供50Mbps~7 Gbps 傳輸能力，可有效的支援愈來愈普及的電腦周邊無線 連結及影音多媒體短距離高速數據傳輸需求。透過802.15.3c 技術，未來高 畫質、高解析度視訊（HD Media）可以直接從HTPC（Home Theater Personal Computer）無線傳輸至顯示設備，利用Wireless HDMI 介面播放; 而更新 iPod、iPhone 或個人行動電腦、PDA 等中的檔案，也不需要透過USB 或網 路線，屆時，整個客廳、或會議室就可擺脫各種資料線的束縛。本子計畫為 研究並設計一次世代嵌入式運算平台（Next-Generation Embedded Computing Platform），並開發先進的SoC 設計流程，在設計初期將利用電子系統層級 （ESL）設計驗證分析與自動化設計整合技術建立虛擬原型（Virtual Prototyping），以配合軟體建置與展現硬體設計的程序。另外將建構一可快速 進行系統處理程序層級（TLM）模型之多核心FPGA 平台，以加速系統晶片 設計及驗證。此次世代嵌入式運算平台搭載異質（Heterogeneous）多處理器 核心，包括(1)中央處理器（MPU）; (2)與中央處理器充分協調溝通之應用服 務處理器（Service Processor, SP）; 以及(3)多個受應用服務處理器管理之高 效能低功率多核心、多執行緒（Multithreaded）數位訊號處理器; (4)高頻寬 Inter-Processor Communication（IPC）Network。本計畫也將設計一可硬體加 速之嵌入式輕量型即時性作業系統（Light-Weight RTOS）來搭配此多核心平 台，支援多任務（Multi-Task）、多率（Multirate）之高效能、低耗能嵌入式 數位訊號處理計算，滿足億級位元傳輸率（Multi-Gbps Data Rate）之無線個 人區域網路（WPAN）應用。 本計畫所設計的 DSP 處理器核心主要是能支援WPAN 基頻運算處理的 要求，其重要的特色有：(1) 32 位元, 2-issue, 具SIMD 與次字元能力, 低於 0.1mW/MOPS 耗能, 高於500MHz@90nm CMOS 效能, 有優良的程式碼密度 以及具架構延展性（包含了Customizable 的指令設計及Configurable Hardware Modules）; (2) 具有架構上的差異性; (3) 具實體操作環境的適應性。本計畫 將提出一套完整的Multi-core Platform-based SoC 設計方法與流程、及其系統 層次的軟硬體分割與界面的自動產生（Interface Auto-generation）。另外，完 整的演算法、架構分析與設計空間探索，及適當的演算法修改及架構轉換， 進而提高實體模組的使用效率，發揮其最大效能，追求速度/功率/面積三者 的最佳化也是本計畫的重點工作。

The IEEE 802.15.3c standard is developing a millimeter-wave-based PHY, which will operate in the new and clear unlicensed band including 57~64GHz, for future wireless personal area network (WPAN). The millimeter-wave WPAN will allow high coexistence with all other microwave systems in IEEE 802.15 and will support 50Mbps~7Gbps high data rate applications, such as high speed internet access, streaming download (VOD, home theater, etc.), real time multiple HDTV video stream, and wireless data bus for cable replacement. In this project, we will develop a high-performance, low-power, programmable, and heterogeneous multi-processor cores SoC platform for multi-Gbps WPAN applications. The heterogeneous multi-core computing platform consists of microprocessor unit (MPU), service processor (SP), scalable and extensible multi-core/multithreading DSPs, specific functional units or hardware accelerator, memory subsystem and DMA, and high bandwidth and efficient inter-processor communication (IPC) network. The major design goals are low power consumption, high performance, and cost effectiveness. Because of the great complexity of the multi-core SoC and the time-to-market consideration, we also develop a rapid FPGA platform: from Matlab/C to TLM-based system prototyping with multi-core FPGA platform for rapid SoC hardware/software co-development. Besides, a heterogeneous multi-core computing virtual platform-driven ESL design methodology is also developed to reduce SoC design cycles. In these three years, we will design a next-generation heterogeneous computing platform with multi-core low-power DSPs and configurable hardware accelerator. The planned DSP processor can support the baseband processing for the multi-Gbps WPAN applications and will be implemented with the SoC design methodology. The main features of the design DSP core include: (1) 32-bit 2-issue data word with SIMD, variable-length instruction, <0.1mW/MOPS, >500MHz@90nm CMOS technology, high code density, and good architecture extensibility, (2) differentiation of the architecture platform, and (3) adaptability of the operating environments (e.g. noise) in wireless communication systems. This project focuses on the complete SoC design methodology including the hardware/software partitioning at the system level with automatic interface generation. Besides, detailed analysis on algorithms and architectures with proper modification and transformation, respectively, to improve the hardware utilization, while optimizing speed, power, and area, is also important in this project. We plan to finish the design of the fast TLM-based system prototyping and an optimal heterogeneous multi-core computing platform with various computing engine. An efficient data transfer with optimal register file and memory subsystem organization is also well developed. Finally, we plan to complete a simple-targeting computing platform with ultra low power consumption through massively parallel computations.