後次微米時代新興電子設計自動化技術之研究---子計畫三：角落錯誤之矽除錯(I)

Abstract

隨著設計複雜度與製程不確定性持續地增加，目前不可能在晶片下線之前完全地驗證設計的功能及效能。目前驗證流程所遺漏的設計錯誤，幾乎都是（1）與時間相關的錯誤（timing-related error），或（2）功能性上複雜的錯誤（complicated functionality error）。這些錯誤僅能在一連串的指令後，才可以被觸發並徵測。目前模擬器（emulation）與模擬技術（simulation），尚無法提供如此高的計算效能（或準確度），以重新產生與矽晶片上相同之錯誤特徵，設計師僅能依靠矽晶片上蒐集到之錯誤回應進行除錯的工作。這種除錯過程被稱為矽晶片除錯（silicon debug）。 在這個子計畫，我們提出了一個可處理功能性錯誤、以及時間相關之錯誤的矽晶片除錯架構。此矽晶片除錯架構包括了三個主要部分：（1）除錯化設計（Design-for-Debug）架構（2）對於多重錯誤（multiple fault）的錯誤區域之鑑定（3）時間函示庫（timing library）錯誤之診斷。 首先，除錯化設計架構需決定那些內部訊號可被除錯硬體所觀察到。其目的在於設計一晶片，使其因設計錯誤所產生之訊號衝突，可以被除錯硬體所觀察到。為了達到此目的，需要一數學上的分析，以估計在給定觀察點之下每個信號可被觀察之機率。此除錯化設計架構為任何後續除錯分析的基礎。 第二，根據經由除錯硬體所觀察到之回應，我們嘗試去鑑定邏輯錯誤可能存在的錯誤區域。與錯誤字典式的偵錯不同（其使用原因-結果方式將錯誤特徵與模擬錯誤進行比對），我們使用結果-原因的方式去大幅度地縮小可能具有邏輯錯誤之區域。此方法並不需要假設錯誤區域的半徑，或是邏輯錯誤的數目。此部分是用於功能性錯誤上之除錯。 第三，我們將目標定在時間相關錯誤之除錯。實際上，這些時間錯誤並沒有被時間分析器（timing analyzer）所回報的一個主要原因，是在於所使用之時間函示庫可能並不完全地正確，導致時間分析的結果並不可靠。邏輯閘型態中一個時間函示庫的錯誤，可能同時地影響在設計中許多信號的時間。因此，第三部分，我們根據邏輯閘型態將邏輯閘延遲錯誤分組，並根據其特徵比對的等級，為每個邏輯閘延遲錯誤的組別進行評分動作。在修改過最高分數的邏輯閘型態之時間表格後，將會重新進行一次動態性的時序分析，並檢查錯誤的反應是否與晶片一致。

As the design complexity and process uncertainty continually increase, it is impossible to completely verify design’s functionality as well as its performance before the tape-out. Those design errors missed by the current verification flow are mostly timing-related errors and complicated functionality errors, which can only be detected after an excessive long sequence of instructions. The current simulation or emulation technique cannot provide such high computation power (or accuracy) to reproduce the true erroneous syndrome in silicon. Thus, designers have to rely on the silicon chips to collect failure responses for debugging. This debugging process is called silicon debug. In this subproject, we propose a silicon-debug framework targeting both functionality errors and timing-related errors. This silicon-debug framework consists of three key components: (1) design-for-debug (DFD) architecture, (2) faulty-region identification for multiple faults, and (3) diagnosis for timing-library errors. First, the DFD architecture needs to determine which internal signals can be observed by the debugging hardware. Its goal is to maximize chip’s capability of identifying a possible value conflict which results from a design error. In order to achieve this goal, a mathematical analysis is required to estimate the probability of each signal being observable with the debugging hardware. This DFD architecture is the fundamental basis for any further debugging analysis. Second, based on the responses observed through the debugging hardware, we attempt to identify the faulty region where the logic errors could locate. Unlike the fault-dictionary diagnosis, which uses a cause-effect approach to match the erroneous syndrome to a modeled fault, we apply an effect-cause approach to gradually shrink the region of the possible logic errors. There is no assumption to the radius of the faulty region or the number of logic faults. This component is built for debugging the functionality errors. Third, we move our target to debug the timing-related errors as well. In reality, one major reason for those timing errors not reported by a timing analyzer is that the timing library in use may not be partially incorrect, which makes the result of timing analysis undependable. One timing-library error of a cell type may affect the timing of several signals in a design concurrently. Therefore, in our third component, we group gate-delay faults based on the gate type and rank each suspect group of gate-delay faults based on its syndrome-matching level. After revising the timing table of the highest-ranked gate type, another dynamic timing analysis will be applied and check if the result matches the chip responses.