奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫五：數位強化式類比數位轉換技術

Abstract

本計畫將研究在奈米CMOS製程下設計高性能的類比數位轉換器（ADC）與數位類比轉換器（DAC）。雖然是混合訊號式積體電路設計，但我們將強調利用數位信號處理（DSP）的技術來彌補先進製程所造成的非理想效應，進而提升整體系統功能或簡化類比電路。簡化後的類比電路將比較容易設計，可隨著技術演化，而且容易在短時間中移植至不同廠商的製程中。 本計畫規劃的研究方向如下：（1）快閃式 ADC；（2）管線式 ADC；（3）二階式 ADC；（4）電流切換式 DAC；（5）時序交錯 ADC；（6）時脈抖動量測及補償。 我們將設計一個 6-Bit 2-GS/s快閃式（Flash）ADC。其中有數位校正式比較器可以降低功率消耗。我們將設計一個 12-Bit 200-MS/s管線式（Pipelined）ADC。我們將簡化運算放大器電路，並發展非線性校正技術來提升解析度。我們將設計一個 10-Bit 100-MS/s二階式（Two-Step）ADC。此 ADC 综合了快閃式 ADC 與管線式 ADC 的設計技術，可以更進一步地降低功率消耗。我們將設計一個 14-Bit 500-MS/s電流切換（Current-Switching）DAC，並且以數位校正方式解決元件匹配問題。 在 ADC 的設計中，除了訊號振幅的解析度，我們還必須留意取樣時序的解析度。例如在時序交錯（Time-Interleaved, TI）ADC 中，取樣相位的不匹配會降低整體 ADC 的解析度。我們將利用前述的 6-Bit Flash ADC 來組合一個 8-channel 6-Bit 16-GS/s TI ADC。而我們將以數位方式來校正取樣相位。另外，高解析度的 ADC 需要有一個低抖動的時脈產生器來產生乾淨的取樣時序。我們則將發展量測時脈抖動的技術，所量測到的時脈抖動資訊可以用來補償 ADC 的數位輸出訊號。如此就不需要一個昂貴的低抖動時脈產生器。 本計畫所設計的電路皆會以 90 nm 或更先進的 CMOS 製作成晶片並加以量測，以驗證所發展的技術的可行性。所發展的晶片都會以「晶片效能指標」（Chip Performance Index, CPI）來和功能類似的晶片相比較。而本計畫的目標就是追求最佳的 CPI。

This project is to design analog-to-digital converters (ADC) and digital-to-analog converters (DAC) in nano-scale CMOS technologies. Although they are mixed-signal designs, we will emphasize the use of digital signal processing to compensate the unfavorable effects on analog circuitry caused by advanced technologies. The objectives are to improve overall all system performance and/or simplify analog circuitry. Simpler analog circuits are easier to design, can scale along with technologies, and take less man-hour to do technology migration. This project is focused on (1) flash ADC; (2) pipelined ADC; (3) two-step ADC; (4) current-switching DAC; (5) time-interleaved ADC; and (6) clock jitter measurement and compensation. We will design a 6-bit 2-GS/s flash ADC. It will include digitally-calibrated comparators to save power. We will design a 12-bit 200-MS/s pipelined ADC. We will simplify the opamp’s circuit, and develop nonlinearity calibration technique to improve ADC’s resolution. We will design a 10-bit 100-MS/s two-step ADC. By combining the design techniques of flash ADC and pipelined ADC, we can further optimize the power consumption of the two-step ADC. We will design a 14-bit 500-MS/s DAC. We will develop digital calibration technique to overcome the limitation due to mismatches. Besides the resolution of signal magnitude, we also must pay attention to the resolution of sampling timing. For example, in time-interleaved (TI) ADCs, mismatches among sampling phases can degrade the ADC’s overall resolution. We will design an 8-channel 6-bit 16-GS/s TI ADC by assembling 8 channels of the 6-Bit 2-GS/s Flash ADC previously mentioned. We will develop calibration technique to correct sampling-phase mismatches. Furthermore, a low-jitter clock is required to provide clean sampling timing for high-resolution ADCs. We will develop technique for clock jitter measurement. We then can use the measured jitter data to compensate the ADC’s digital outputs, thus avoiding the use of expensive low-jitter clocks. All circuits designed in this project will be fabricated using 90nm or more advanced CMOS technologies. The chips will be characterized to validate the design techniques developed in this project. We will compare the chips with similar designs against the chip performance index (CPI). Our objective is to achieve the best CPI.