奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫三：奈米CMOS技術之60∼110-GHz射頻前端關鍵性積體電路之研究與設計

Abstract

應用於傳遞高品質視訊影像的家用無線網路在不久的將來將變的普及，高速以及高 資料量的傳送，將使區域性的寬頻無線通訊系統的需求更為提高。因此，如何設計應用 於更高操作頻段的無線傳輸系統，如60~110-GHz 之V-Band 與W-Band 之區域性無線通 訊系統，將是一個重要的研究主題。 隨著CMOS 製程由深次微米(deep submicron)進步到奈米(nanometer)，電晶體的最高 操作頻率(ft)已超過100GHz，使用奈米CMOS 製程，設計操作頻率在60~110-GHz 之 V-Band 與W-Band 的射頻積體電路已經可望實現。 本計畫將以130nm ~ 45nm之奈米CMOS技術來研究並設計操作頻率在60~110-GHz 的高頻段無線通訊收發器之前端主要電路元件。首先將以130-nm 與90-nm CMOS 製程 技術，設計操作頻率於60 GHz 的V-Band 射頻前端接收器與發射器電路；延續設計 60-GHz 頻段之前端電路的知識，設計應用於W-Band 頻帶之窄頻與寬頻之射頻前端接 收器與發射器之主要關鍵電路。此外，本計畫也將針對所設計的V-Band 與W-Band 射 頻關鍵性電路進行低功率以及高性能的改善，使電路在高頻操作下具有高性能外，亦能 具有低電壓低功率消耗的特性。此外，亦將進行前瞻性研究，以創新的觀念設計電路， 期望能將各主要的前端電路元件之性能推至極限。 預計完成的主要前端電路元件有：低雜訊放大器、混波器、震盪器、除頻器以及功 率放大器；各元件的功能及設計考量簡述如下: 1. 低雜訊放大器 (Low-Noise Amplifier)： 低雜訊放大器的目的在於提供足夠的增益以及低的雜訊指數(NF)，以降低後級 電路對雜訊的影響，對整個系統的靈敏度有決定性的影響。此計畫除了針對雜訊指 數的特性改善外，也將設計使其有較低的功率消耗。 2. 混波器 (Mixer)： 混波器目的在將射頻訊號與本地震盪訊號相乘，使訊號頻率降至中頻或基頻； 或將中頻或基頻訊號與本地振盪訊號相乘，使訊號升至為射頻訊號。設計上為了使 系統的動態範圍提高，混波器需有足夠的線性度(linearity)，以提高動態區間(dynamic range)。 3. 震盪器(VCO)： 震盪器目的是產生本地震盪訊號，提供混波器將訊號進行升降頻使用。設計上，震盪器需要有好的相位雜訊(phase noise)，高頻率調整範圍，以及低功率的特 性。 4. 除頻器(Frequency Divider) 高頻除頻器為頻率合成器中的一個重要元件，此電路將震盪器的輸出頻率先行 除頻，以使後端的電路處理較為低頻率的訊號，進而降低整體的功率消耗。此高頻 除頻器在設計上，要能處理寬頻的輸入訊號，同時低功率消耗也是重要的考量。 5. 功率放大器 (Power Amplifier)： 功率放大器的目的在將射頻訊號放大並驅動天線將訊號發射出去，為使訊號在 傳遞時減少失真，以及降低功率消耗，功率放大器需有優良的功率效益以及好的線 性度。 在實現及量測驗證過此計畫中之各元件的功能後，將進一步與其他子計畫成果整 合，以應用於無線通訊之收發器系統，並同時改善各電路元件的特性。預計此三年期間 完成多個主要關鍵性的電路方塊，以運用於未來的57~64-GHz 頻段以及75~110-GHz 之 無線通訊傳送接收機與傳送機之使用；同時，本三年型研究計畫也將整合已開發的 60-GHz 頻段之關鍵性主要電路，並實現57~64-GHz 之V-Band 寬頻無線通訊系統，並 將此系統實際地應用在高速高資料量的訊息傳輸上。

In the foreseeable future, the application of home RF, wireless video transmission for example, will become popular. Broadband wireless local area network for much higher speed and higher data rate transmission will be substantially demanded. Therefore, it will become a significant research topic to design a wireless communication system operating in much higher frequency, such as V-Band and W-Band wireless local area network in the frequency ranging from 60 GHz to 110 Ghz, so that high data rates can be achieved. With the development of the CMOS technology which moves from deep sub-micron to nanometer scale, the maximum operating frequency, ft, of the MOS transistor has gone beyond 100 GHz. Consequently, it is realizable to implement the CMOS RF front-end circuits operating in the V-Band and W-Band which are within 60~110-GHz by nanometer CMOS process. The purpose of this project is to develop the key components in wireless transceiver front-end circuits by 130~45nm nanometer CMOS process for the frequency band from 60 GHz to 110 GHz. In the beginning, the key components of 60-GHz transceiver front-end circuits will be designed by 130-nm and 90-nm CMOS processes. Based on the knowledge of the designed 60-GHz circuits, the circuits operating in the W-Band (75~110-GHz) will be designed and implemented. Besides, the circuits will not only be designed for high frequency but will be improved to dissipate lower power. Novel concepts of circuit designs will be investigated to drive the circuits to their utmost. In this project, the front-end circuits to be accomplished are low noise amplifier (LNA), mixer, voltage-controlled oscillator (VCO), divider, and power amplifier (PA). The functions and design considerations of each circuit blocks are described as follows 1. LNA: The aims of the LNA are to provide sufficient gain and low noise figures (NF) so that the following stage can have less influence on noise. The LNA mainly decide the sensitivity of the system. The LNA in this project will be designed to achieve low noise performance, and will be also designed to dissipate lower power. 2. Mixer: The mixers, which function as multipliers, multiply the RF or BB signals with LO signal. Down (Up)-convert the signal frequency of RF (BB) to BB (RF). The former is called downconversion, and the later is called up-conversion. Sufficient linearity should be provided to extend the dynamic range of the system. 3. VCO: The aims of the VCO are to provide LO signal for the up/down-conversion mixers. Better phase-noise, wide frequency tuning range, and low power dissipations are the typical design considerations. 4. Divider: The high frequency divider is an important function block of frequency synthesizers. The dividers divide the high frequency LO from VCO first. The following program counters can be operated in lower frequency, and consequently the power dissipation can be save more. The high frequency divider should be designed to handle input signals with wide frequency range. Low power dissipation is another main design consideration. 5. PA: The power amplifier is used to amplify the RF signal and to drive the antenna. The RF signal is then transmitted through the antenna. To reduce the signal distortions and decrease power consumptions, better power efficiency and sufficient linearity are required when designing the PA. After realized, measured and verified each function block in this project, these key components are going to be integrated with other achievements of the sub-projects to demo a system of wireless communication. Meanwhile, the performance of each circuit will be improved further. Within this three-year project, several RF key circuits with silicon proved are going to be realized, and can be applied to implement 57~64-GHz and 75~110-GHz wireless transceivers in the future. In this 3-year research project, the developed 60-GHz circuit blocks will also be applied to realize 57~64-GHz wide-band wireless communication system. Besides, the practical high speed and high data-rate transmission will be demonstrated by this 57~64-GHz transceiver.