系統層級之多核心嵌入式系統發展與驗證環境---子計畫三：多核心嵌入式系統效能與耗能分析監測與改善(I)

Abstract

近年來隨著嵌入式系統晶片功能越益強大，嵌入式系統晶片也漸漸朝向複雜之多 核心設計以提升效能、降低耗能與成本。然而傳統多核心嵌入式系統晶片設計方法及 工具多半針對已完成之系統晶片進行效能與耗能的評估，對於設計初期或設計的過程 中所能得到的效能與耗能參數所知有限，也無法有效的在設計中期或初期，偵測出多 核心嵌入式系統晶片可能遭遇的軟硬體效能與耗能問題，更無法有效透過軟體或硬體 技術來改善。因此本子計畫的主要目的在於設計多核心嵌入式系統晶片之效能與耗能 分析與監測軟硬體擴充模組以及工具，以協助多核心嵌入式系統晶片與軟體設計者， 在設計期間藉由多核心嵌入式效能與耗能分析與監測軟硬體之擴充，取得系統效能與 耗能資訊，透過工具的分析，事先掌握多核心嵌入式系統晶片硬體與軟體的效能與耗 能特性，進而在軟、硬體設計層面加以改進。本子計畫規劃以兩年時間研究多核心嵌 入式系統晶片之效能與耗能分析、監測與提升技術，計畫第一年將設計效能與耗能硬 體元件與軟體來協助效能與耗能工具，以達到效能與耗能之分析、監測，進而協助設 計者改善多核心系統晶片與軟體。計畫第二年則利用第一年多核心嵌入式效能與耗能 分析與監測軟硬體之擴充，取得系統效能與耗能動態資訊，透過動態回受控制的技術， 與子計畫合作開發多核心嵌入式系統晶片之高效能、低耗能動態管理技術，並透過前 述工具加以分析、評估與驗證。

Multi-core embedded systems and system on chips (SoCs) which achieve a higher performance and a better cost- and energy-efficiency than single-core embedded systems become more and more popular recently. Unfortunately, conventional approaches for optimizing performance and energy consumption of multi-core SoCs rely on fine tuning after the hardware (H/W) and software (S/W) are completely developed. It is very difficult for system and software engineers to identify potential H/W and S/W performance and power consumption problems while the system is being developed. The problem makes multi-core SoCs very difficult to design and optimize. In this project, performance and power consumption profiling and monitoring hardware and software extensions and tools for multi-core embedded systems and SoCs are proposed. The tools closely working together with the proposed performance and energy profiling hardware and software components which provide the performance and power consumption monitoring and profiling of multi-core SoCs facilitate system and software designers to diagnose performance and power consumption problems and bottlenecks while the system is being developed. Based on these performance and power consumption analyses and results, system and software designers can optimize multi-core embedded SoCs during design phase. In the first year, hardware and system software components are added to the target multi-core embedded system and SoC to support real-time performance and power consumption monitoring. Based on the results collected in the first years and the profiling hardware and softare, this subproject will work together with other subprojects to propose and evaluate high performance and low power designs for multi-core embedded SoCs based on dynamic feedback control mechanisms.