高效能3D繪圖處理器關鍵技術之研究

Abstract

3D電腦繪圖技術快速發展，下一代的3DMark06程式，已大量採用含有HDR-high dynamic range技術及Microsoft Shader Model 3.0標準的測試項目。概而言之，GPU (graphics processing unit) 架構與相關技術將持續成為未來重要的研究議題。在使用者對於畫面細緻擬真的更高需求下，整個shading system的功能必須更加擴充。硬體技術方面，將面對處理更多的vertices與fragments、更複雜的multi-thread/multi-pass rendering 程式、更大量的HDR資料運算，與更多中間值資料存取等問題；另外，支援HDR浮點處理與SM3.0條件分支指令等相關技術，已為新一代GPU的必備條件。軟體技術方面，則將面臨threads/passes 的切割、指令平行度的開發、registers的使用、以及資料壓縮等問題。本計畫擬以3D繪圖管線流程的角度出發，規劃為期三年的研究，以探討3D繪圖技術所面臨的各項軟硬體研究議題。 本三年期計畫申請案的研究內容將以發展3D繪圖技術為目的，並依編譯技術(屬程式執行前的處理)、處理器架構技術(屬程式執行期間的處理)、及資料緩衝儲存技術等三大領域，規劃各項研究主題，概述如下︰ 領域一︰編譯技術— 3D繪圖應用程式在編譯為組合語言程式時，傳統上面臨的主要困難有硬體資源有限，程式／指令執行時間不固定、暫存器使用率不佳等。因此我們擬進行以下主題之研究︰ 主題一、提升像素著色器效率的指令排程技術(之大部份內容) 主題二、像素著色器中的暫存器使用技術(之大部份內容) 領域二︰處理器架構技術— 繪圖處理的運算過程中，除了運算量極大，還包含了資料量極大，硬體資源需求變化極大，以及運算延遲時間變化極大等特性。因此我們擬進行以下主題之研究︰ 主題一、提升像素著色器效率的指令排程技術(之部份內容) 主題二、像素著色器中的暫存器使用技術(之部份內容) 主題三、可動態重組之著色單元及頂點與像素的負載平衡技術 主題四、材質過濾處理之可重組單元設計及負載平衡技術 主題五、提前深度測試與階層式深度測試資料不一致性之研究 領域三︰資料緩衝儲存技術— 在繪圖處理管理線中，應有的資料記憶體一般包含處理器暫存器檔、Z buffer、texture memory、frame buffer、以及stencil buffer。另外為因應多緒執行、多pass執行、deferred shading 等需求，中間值大量出現，又需另外尋找記憶空間 (例如F-buffer、G-buffer)、妥善管理，並融合入系統設計中。因此我們擬進行以下主題之研究︰ 主題六、可變長度資料壓縮檔中快速索引技術 主題七、繪圖管線中資料與中間值的管理技術 主題八、可共享及可延展的暫存器檔設計 我們基於計算機架構及編譯技術的既有知識基礎，期望能將之應用於發展關鍵的3D繪圖處理軟、硬體技術，以達3D電腦繪圖更快、更擬真、更省、以及更具彈性等目的。預計本計畫執行完畢時，將有助提昇我國graphics處理的設計開發能力及經濟利益。該等技術對數位生活、醫療照護等，均有助長促成之功。此計畫所規劃的研究是目前產學研的重要趨勢，也適合國內數位設計、SoC等工業發展的人才培育所需。 備註︰本申請案研究內容符合國科會工程處資訊學門所規劃之學門重點研究項目︰ 「資訊工程(一)學門重點規劃主題： (1) 前瞻性系統單晶片架構： 主要研究課題e：可重組式計算 主要研究課題g：低儲存及傳輸量程式及資料壓縮技術」 等項目及 「資訊工程(二)學門重點規劃主題： (1) 服務導向計算與應用： 3.科技化服務致能(enabling)核心技術： d.媒體處理（media processing）」項目。 參考網址︰ http://www.nsc.gov.tw/eng/disp_adv.asp

3D computer rendering techniques are progressing very rapidly. The 3DMark06 benchmarks have used extensive HDR—high dynamic range techniques and test items revealed in Microsoft Shader Model 3.0. All these indicate that GPU (graphics processing unit) architecture and its related processing will continue to be important research issues. With users』 increasing demands for finer details and more realism, functionalities of a shading system must keep expanding. On the hardware side, the rendering system must be able to process more vertices and fragments, complex multi-threaded/multi-pass rendering programs, more HDR data and computations, and more intermediate values; furthermore, floating-point support for HDR and conditional instructions for Shader Model 3.0 are becoming necessary. On the software side, it must face issues such as thread/pass partitioning, instruction-level parallelism exploitation, register usage, and data compression. This proposal bases on the rendering pipeline flow and explores the important software/hardware 3D graphics rendering techniques, in a three-year research effort. The objective of this three-year research proposal is to explore key 3D graphics rendering techniques. We categorize such techniques into three domains: compilation techniques (before-program-execution processing), processor architecture techniques (during-program-execution processing), and data buffering/storage techniques. Each contains a number of research topics, as described below: Domain 1: Compilation techniques—Conventional difficulties faced with a compiler for 3D rendering include limited hardware resources, fluctuating code or instruction execution times, and poor register usages. We intend to study the following topics: Topic 1: Instruction scheduling techniques for efficient pixel shader (most of its contents) Topic 2: Register usage techniques in pixel shader (most of its contents). Domain 2: Processor architecture techniques—Features observed during the rendering process include vast amount of computation, vast amount of data, sharply varying needs for hardware resources, and sharply varying operation latencies. We intend to study the following topics: Topic 1: Instruction scheduling techniques for efficient pixel shader (some of its contents) Topic 2: Register usage techniques in pixel shader (some of its contents) Topic 3: Reconfigurable shader design and vertex/pixel load balancing techniques Topic 4: Reconfigurable texture filter design and load balancing techniques Topic 5: Study of data inconsistency due to pre-Z test and use of hierarchical Z buffer. Domain 3: Data buffering/storage techniques—In a rendering pipeline, data storages that typically exist include processor register file, Z buffer, texture memory, frame buffer, and stencil buffer. Furthermore, to facilitate multi-threading, multi-pass execution, deferred shading, etc., large amounts of intermediate data emerge. Additional storages (such as F-buffer and G-buffer) are hence mandatory, require delicate management, and must be integrated into the system properly. We intend to study the following topics: Topic 6: Fast indexing technique for variable-length data compression Topic 7: Data and intermediate value management techniques in graphics rendering pipeline Topic 8: Design of a sharable and stretchable register file. We hope to extend our expertise in computer architecture and compilation techniques to explore these key software/hardware techniques in 3D graphics rendering. Achieving the goals set forth in this proposal will enable 3D rendering to be faster, more realistic, less costly, and more flexible. It is expected that upon successful completion of projects of such kind, our domestic capacity in graphics processor designs and business revenues can be greatly upgraded. The techniques to be developed will also facilitate the realization of digital life and medical caring. This proposal complies with the both essential industrial and research trends, and its execution will certainly produce a good number of urged quality researchers in digital design and SoC development. Note: Contents of this proposal comply with these key promotional research topics as outlined by the Information Engineering Discipline, Engineering Division, National Science Council: 「Information Engineering (I) key promotional research topics: (1) Advanced SoC architecture: Major topic e: reconfigurable computing Major topic g: low storage and bandwidth programming and data compression techniques」, and 「Information Engineering (II) key promotional research topics: (1) Service oriented computing and applications: 3. Technological services enabling core techniques: d. Media processing」. Reference web site: http://www.nsc.gov.tw/eng/disp_adv.asp