適用於無線視訊娛樂之多系統融合及節能技術---子計畫五：適用於無線視訊娛樂之新世代可調式視訊技術研究(I)

Abstract

隨著在視訊技術、網路、和計算能力的快速進展，透過無線網路傳送的視訊娛樂應 用，也越來越重要。然而，無線網路的連線協定多樣化，頻寬變化相當大，不利確保視 訊娛樂的傳送品質，此外，視訊娛樂內容可能由各種不同能力的終端設備做存取，小如 只具備小螢幕、有限計算能力與電力的手機，大至功能強大的高畫質電視，所需計算能 力、記憶體大小、頻寬分配與傳輸保護也大不相同。為滿足此需求，MPEG 和ITU-T 擴 展MPEG-4 AVC/H.264 成為scalable video coding (SVC)。然而，雖然SVC 的multi-layer structure 可帶來種種好處達成有效率的壓縮，卻也為SVC 帶來比已經相當複雜的H.264 還要高上數倍的計算量與記憶體存取，因此，如何以硬體實現加速運算，為目前相當重 要之研究方向。 本計畫將開發基於H.264/AVC 的SVC 矽智財技術，包含了baseline profile 和high profile。目標應用為在透過無線傳輸的低功耗手持行動裝置(baseline profile@640×480× 30fps)，或是HDTV (high profile@1280×720×30fps)的視訊娛樂服務，並能根據目前頻寬 和電力狀況調整視訊編解碼，以達最佳的觀賞品質。由於SVC 具有畫面大小、畫面速 率與SNR 可調適性，如何處理這些可調適性帶來的複雜度與資料相依性，適當安排硬 體排程，為一研究重點。此外，配合多變的無線網路，納入channel coding 的保護至video coding 整體考量，依據不同layer 重要性給與不同保護，使達成最佳rate distortion。而 由於此設計可以應用在可攜式裝置或是被整合在更複雜的SoC 設計內，設計低功率架構 或發展適合硬體的快速演算法減少功率消耗也將是一個很重要研究重點。由於視訊資料 龐大，60%功率消耗是記憶體上，因此在設計重點將特別考量降低記憶體存取需求和緩 衝器大小，並以此為準則設計datapath。最後為完整驗證欲達成的功能與耗電量，將以 晶片製作驗證設計。

With the rapid advances in video coding technology, network infrastructure, and computing power, wireless video entertainment becomes more and more important. However, the wireless channels have varying connection quality and protocol, which is not suitable to ensure video quality. Moreover, the source content could be accessed by versatile devices with capabilities from cellular phones with limited display and battery to powerful high definition TV. To fulfill such requirements, MPEG and ITI-T have extended the well-known H.264 to be a scalable video codec system. However, though multi-layer structure in scalable video brings a lot of benefits, they also introduce much higher complexity in both encoder and decoder than current quite complex H.264 video codec. Thus, how to accelerate this video codec with hardware is an important research topic for real time applications. This project is to develop a low power scalable video codec based on scalable extension of H.264. The target application could be the low power mobile handset (baseline profile@ 640x480x30fps of SVC) or HDTV entertainment applications (high profile@1280x720x30fps of SVC). For such applications, the target is graceful quality degradation according to the available bandwidth and battery power. In addition, the scalable video codec will have spatial, temporal and SNR scalabilities. All these scalabilities impose a great challenge to hardware scheduling design due to its dramatic complexity and data dependencies, which will be the focus of our research. Besides, this design will be implemented as a silicon intellectual property to be reusable in a full video system. This design will be implemented as an IP for reuse convenience. Since this IP will be used in portable application or integrated into a larger SOC environment, how to reduce power consumption by low power architecture or hardware oriented fast algorithm is also an important research focus. In which, due to large amount of video data, over 60% of power will be consumed in memories. Thus, the whole design will focus on efficient and effective memory access and size, and use it as a guideline for the datapath design. Finally, to ensure the design completeness, a chip will be implemented for functional and power verification.