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dc.contributor.authorWang Pei-Yuen_US
dc.contributor.authorTsui Bing-Yueen_US
dc.date.accessioned2014-12-16T06:13:47Z-
dc.date.available2014-12-16T06:13:47Z-
dc.date.issued2014-10-07en_US
dc.identifier.govdocH01L021/70zh_TW
dc.identifier.govdocH01L029/78zh_TW
dc.identifier.govdocH01L029/10zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104337-
dc.description.abstractAn enhanced tunnel field effect transistor includes a substrate, a layer of P-I-N structure, a hetero-material layer, a gate dielectric layer, a gate structure and a spacer, in which the layer of P-I-N structure is disposed on the substrate, the hetero-material layer is disposed on portion of the layer of P-I-N structure, the gate dielectric layer is disposed on the hetero-material layer, the gate structure is disposed the gate dielectric layer and a spacer is disposed on a sidewall of the hetero-material layer, the gate dielectric layer, and the gate structure. The hetero-material layer can increase the tunneling efficiency of the enhanced tunnel field effect transistor to increase the conductor current to improve the enhanced tunnel field effect transistor performance.zh_TW
dc.language.isozh_TWen_US
dc.titleEnhanced tunnel field effect transistorzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08853824zh_TW
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