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dc.contributor.authorJou Shyh-Jyeen_US
dc.contributor.authorTu Ming-Hsienen_US
dc.contributor.authorHu Yu-Haoen_US
dc.contributor.authorChuang Ching-Teen_US
dc.contributor.authorChiu Yi-Weien_US
dc.date.accessioned2014-12-16T06:13:48Z-
dc.date.available2014-12-16T06:13:48Z-
dc.date.issued2014-09-16en_US
dc.identifier.govdocG11C011/00zh_TW
dc.identifier.govdocG11C011/412zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104344-
dc.description.abstractA static memory and a static memory cell are provided. The static memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a first pull-down switch, and a second pull-down switch. When a data writing operation is performed, the latching capability of the latch circuit constituted by the first to the sixth transistors is disabled by turning off the second transistor or the fifth transistor, so that the speed of the data writing operation is increased and the data writing performance is improved. The first switch and the second switch provide a path for reading or writing data, and the third switch is coupled to a bit line for receiving data from or transmitting data to the bit line.zh_TW
dc.language.isozh_TWen_US
dc.titleStatic memory and memory cell thereofzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber08837207zh_TW
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