完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee Chen-Yi | en_US |
dc.contributor.author | Yu Chien-Ying | en_US |
dc.contributor.author | Yu Chia-Jung | en_US |
dc.date.accessioned | 2014-12-16T06:14:01Z | - |
dc.date.available | 2014-12-16T06:14:01Z | - |
dc.date.issued | 2013-06-18 | en_US |
dc.identifier.govdoc | H03B001/00 | zh_TW |
dc.identifier.govdoc | H03K003/00 | zh_TW |
dc.identifier.govdoc | H03H011/26 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104474 | - |
dc.description.abstract | A delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Delay cell and digitally controlled oscillator | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 08466729 | zh_TW |
顯示於類別: | 專利資料 |