標題: Operating method and circuit for low density parity check (LDPC) decoder
作者: Liu Chih-Hao
Liao Yen-Chin
Lee Chen-Yi
Chang Hsie-Chia
Hsu Yarsun
公開日期: 31-一月-2012
摘要: An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.
官方說明文件#: G06F011/00
H03M013/00
URI: http://hdl.handle.net/11536/104614
專利國: USA
專利號碼: 08108762
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