完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Meng | en_US |
dc.contributor.author | Hsin-Fei | en_US |
dc.contributor.author | Horng | en_US |
dc.contributor.author | Sheng-Fu | en_US |
dc.contributor.author | Chao | en_US |
dc.contributor.author | Yu-Chiang | en_US |
dc.date.accessioned | 2014-12-16T06:14:26Z | - |
dc.date.available | 2014-12-16T06:14:26Z | - |
dc.date.issued | 2010-04-06 | en_US |
dc.identifier.govdoc | H01L029/66 | zh_TW |
dc.identifier.govdoc | H01L029/08 | zh_TW |
dc.identifier.govdoc | H01L035/24 | zh_TW |
dc.identifier.govdoc | H01L051/00 | zh_TW |
dc.identifier.govdoc | H01L021/331 | zh_TW |
dc.identifier.uri | http://hdl.handle.net/11536/104727 | - |
dc.description.abstract | A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process. | zh_TW |
dc.language.iso | zh_TW | en_US |
dc.title | Vertical organic transistor | zh_TW |
dc.type | Patents | en_US |
dc.citation.patentcountry | USA | zh_TW |
dc.citation.patentnumber | 07692269 | zh_TW |
顯示於類別: | 專利資料 |