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dc.contributor.author陳冠能en_US
dc.contributor.author賴明芳en_US
dc.contributor.author陳宏明en_US
dc.date.accessioned2014-12-16T06:14:35Z-
dc.date.available2014-12-16T06:14:35Z-
dc.date.issued2013-11-21en_US
dc.identifier.govdocH01L027/04zh_TW
dc.identifier.govdocH02H009/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104820-
dc.description.abstract一種三維積體電路的靜電放電防護結構,包括一第一主動層、一矽晶穿孔元件以及一第二主動層。其中矽晶穿孔元件配置於第一主動層中,第二主動層則與第一主動層相互堆疊。第二主動層包括一基板以及一靜電放電保護元件,靜電放電保護元件具有一摻雜區埋於基板內,且靜電放電保護元件電性連接該矽晶穿孔元件。zh_TW
dc.language.isozh_TWen_US
dc.title三維積體電路的靜電放電防護結構zh_TW
dc.typePatentsen_US
dc.citation.patentcountryTWNzh_TW
dc.citation.patentnumberI416706zh_TW
Appears in Collections:Patents


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