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dc.contributor.authorJIANG Hiu-Ruen_US
dc.contributor.authorYANG Yu-Mingen_US
dc.contributor.authorHO Sung-Tingen_US
dc.date.accessioned2014-12-16T06:14:45Z-
dc.date.available2014-12-16T06:14:45Z-
dc.date.issued2014-09-11en_US
dc.identifier.govdocG06F017/50zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/104872-
dc.description.abstractAn ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load/buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design.zh_TW
dc.language.isozh_TWen_US
dc.titleENGINEERING CHANGE ORDER HOLD TIME FIXING METHODzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20140258957zh_TW
Appears in Collections:Patents


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