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dc.contributor.authorLEE Chen-Yien_US
dc.contributor.authorYU Chien-Yingen_US
dc.contributor.authorYU Chia-Jungen_US
dc.date.accessioned2014-12-16T06:15:01Z-
dc.date.available2014-12-16T06:15:01Z-
dc.date.issued2013-02-14en_US
dc.identifier.govdocH03K005/06zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105074-
dc.description.abstractA delay cell includes a first inverted transistor pair, a second inverted transistor pair and a plurality of delay units. The first inverted transistor pair is used to receive an input signal. The second inverted transistor pair is electrically cross-coupled to the first inverted transistor pair and cross-controlled by the first inverted transistor pair. The delay units are cascaded between the first inverted transistor pair and between the second inverted transistor pair, thereby providing a plurality of signal propagation delays sequentially, wherein the input signal is delayed for a pre-determined time by the first inverted transistor pair, the second inverted transistor pair and the delay units which are operated sequentially, thereby creating an output signal corresponding to the pre-determined time. A digitally controlled oscillator including the aforementioned delay cells is provided.zh_TW
dc.language.isozh_TWen_US
dc.titleDelay Cell and Digitally Controlled Oscillatorzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20130038369zh_TW
Appears in Collections:Patents


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