完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lo, Tien-Yu | en_US |
dc.contributor.author | Hung, Chung-Chih | en_US |
dc.date.accessioned | 2014-12-08T15:14:25Z | - |
dc.date.available | 2014-12-08T15:14:25Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-1359-1 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/10988 | - |
dc.description.abstract | A continuous-time 4th-order equiripple linear phase G.-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3dB cutoff frequency is 1GHz with the group delay less than 4% variation up to 1.5fc frequency. The -43dB of IM3 at filter cutoff frequency is obtained with -4dbm two tone signals. Implemented in 0.18-mu m CMOS process, the chip occupies 1mm(2) and consumes 175mW at a 1.5-V supply voltage. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 1 GHz OTA-Based low-pass filter with a high-speed automatic tuning scheme | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS | en_US |
dc.citation.spage | 408 | en_US |
dc.citation.epage | 411 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000253273200103 | - |
顯示於類別: | 會議論文 |