Parallel pixel processing using programmable gate arrays

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DC 欄位	值	語言
dc.contributor.author	Budgett, DM	en_US
dc.contributor.author	Tang, PE	en_US
dc.contributor.author	Sharp, JH	en_US
dc.contributor.author	Chatwin, CR	en_US
dc.contributor.author	Young, RCD	en_US
dc.contributor.author	Wang, RK	en_US
dc.contributor.author	Scott, BF	en_US
dc.date.accessioned	2014-12-08T15:02:25Z	-
dc.date.available	2014-12-08T15:02:25Z	-
dc.date.issued	1996-08-15	en_US
dc.identifier.issn	0013-5194	en_US
dc.identifier.uri	http://hdl.handle.net/11536/1105	-
dc.description.abstract	A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel processing paths in programmable gate arrays, a wide range of image processing algorithms can be implemented in realtime.	en_US
dc.language.iso	en_US	en_US
dc.subject	programmable logic devices	en_US
dc.subject	image processing	en_US
dc.subject	parallel algorithms	en_US
dc.title	Parallel pixel processing using programmable gate arrays	en_US
dc.type	Article	en_US
dc.identifier.journal	ELECTRONICS LETTERS	en_US
dc.citation.volume	32	en_US
dc.citation.issue	17	en_US
dc.citation.spage	1557	en_US
dc.citation.epage	1559	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1996VF33600023	-
dc.citation.woscount	5	-
顯示於類別：	期刊論文

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