A 61 MHz 72K gates 1280x720 30FPS H.264 intra encoder

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Li, De-Wei	en_US
dc.contributor.author	Ku, Chun-Wei	en_US
dc.contributor.author	Cheng, Chao-Chung	en_US
dc.contributor.author	Lin, Yu-Kun	en_US
dc.contributor.author	Chang, Tian-Sheuan	en_US
dc.date.accessioned	2014-12-08T15:14:46Z	-
dc.date.available	2014-12-08T15:14:46Z	-
dc.date.issued	2007	en_US
dc.identifier.issn	1520-6149	en_US
dc.identifier.uri	http://hdl.handle.net/11536/11157	-
dc.description.abstract	This paper presents an HD720p 30 frames per see H.264 intra encoder operated at 61MHz with just 72K gate count. We achieve the low cost and low operating frequency with the highly utilized variable pixel scheduling, and a modified three-step fast algorithm. Thus, the resulted design only needs half of operating frequency and reduces 30% of area cost compared to the previous HD720p intra encoder design.	en_US
dc.language.iso	en_US	en_US
dc.subject	intra prediction	en_US
dc.subject	H.264	en_US
dc.title	A 61 MHz 72K gates 1280x720 30FPS H.264 intra encoder	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2007 IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol II, Pts 1-3	en_US
dc.citation.spage	801	en_US
dc.citation.epage	804	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000248908100201	-
顯示於類別：	會議論文