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dc.contributor.authorHung, Jui-Huien_US
dc.contributor.authorChen, Sau-Geeen_US
dc.date.accessioned2014-12-08T15:15:20Z-
dc.date.available2014-12-08T15:15:20Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1834-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/11512-
dc.description.abstractIn this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.18 mu m process technology.en_US
dc.language.isoen_USen_US
dc.subjectLDPC codeen_US
dc.subjectdecoderen_US
dc.subjectarchitectureen_US
dc.titleA 1.45Gb/s (576,288) LDPC decoder for 802.16e standarden_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND INFORMATION TECHNOLOGY, VOLS 1-3en_US
dc.citation.spage219en_US
dc.citation.epage224en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000256344200040-
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