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dc.contributor.authorLin, You-Hsienen_US
dc.contributor.authorLo, Shih-Linen_US
dc.contributor.authorLai, Wei-Chien_US
dc.contributor.authorJuan, Ta-Yangen_US
dc.contributor.authorHsu, Terng-Yinen_US
dc.date.accessioned2014-12-08T15:16:30Z-
dc.date.available2014-12-08T15:16:30Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0582-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/12200-
dc.description.abstractTiming synchronization is an important component in a receiver designed to recover data form sampling digital waveform. A synchronous sampling recovery with dual correlator differential (DCD) based acquisition with effects of auto-gain controller (AGC) is proposed to achieve fast timing acquisition for direct sequence / code division multiple access (DS/CDMA) system over frequency-selective fading channel in this paper. It measures both received DCD difference power to determine the good sampling phase from an all-digital phase interpolator based multiphase generator. This solution can tolerate 50ppm system clock offset (SCO) under frequency-selective fading channel. Hence, we not only to determine the good sampling phase fast, but also to arrive stable variable gain amplifier (VGA) with AGC controller in DS/CDMA system approaches.en_US
dc.language.isoen_USen_US
dc.subjecttiming recoveryen_US
dc.subjectsynchronizationen_US
dc.subjectphase interpolatoren_US
dc.subjectmultiphaseen_US
dc.titleSynchronous sampling and SNR-based gain control in DS/CDMA systemsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papersen_US
dc.citation.spage136en_US
dc.citation.epage139en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000247000000034-
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