標題: | An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids |
作者: | Ou, Shih-Hao Chang, Kuo-Chiang Liu, Chih-Wei 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Static floating-point arithmetic;Cascaded datapath;Linear-phase FIR filter;Hearing aid;ANSI S1.11 1/3-octave filter bank |
公開日期: | 1-一月-2015 |
摘要: | The main contribution of this study is the development of an area-/energy-efficient cascaded direct-truncation (DT) datapath with the so-called static floating-point (SFP) arithmetic to realize a low-delay analysis filter bank (AFB) for digital hearing aids. In the proposed SFP LPFIR (linear-phase finite impulse response) filter engine, lower silicon area and lesser power consumption facilitate better SNR performance than that achieved with the conventional post-truncation (PT) datapath with integer arithmetic. Moreover, in the proposed LPFIR filter engine, a cascaded 16-bit SFP A-M-S-Acc datapath is used that consists of two embedded 1-bit shifters to improve hardware usage and parallelism, one 16-bit DT adder (A), one 16-bit DT multiplier (M), one 16-bit barrel shifter (S), and one 16-bit DT accumulator (Acc). The operations per cycle (OPC) of the proposed SFP LPFIR filter engine reaches 6, which enables efficient fabrication of the low-latency AFB for hearing aids. To verify the effectiveness of the proposed 16-bit SFP LPFIR filter engine, a 10-ms 18-band quasi-ANSI S1.11 1/3-octave AFB for digital hearing aids was implemented using UMC 90-nm CMOS technology. The AFB was operated at 792 kHz to process, in real-time, 24 kHz audio, with the power consumption being approximately 80.6 mu W (at 1 V). Compared to the previous design in which the conventional PT datapath with integer arithmetic was used, approximately 9.6% of total power and 83% of silicon area were saved and almost the same SNR (signal-to-noise ratio) performance was achieved with the new system, when evaluated by a 3.96-s sequence of Mandarin speech. (C) 2014 Elsevier B.V. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.vlsi.2014.06.004 http://hdl.handle.net/11536/123853 |
ISSN: | 0167-9260 |
DOI: | 10.1016/j.vlsi.2014.06.004 |
期刊: | INTEGRATION-THE VLSI JOURNAL |
Volume: | 48 |
起始頁: | 230 |
結束頁: | 238 |
顯示於類別: | 期刊論文 |