完整後設資料紀錄
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dc.contributor.authorCheng, Chun-Huen_US
dc.contributor.authorHsu, Hsiao-Hsuanen_US
dc.contributor.authorChou, Kun-Ien_US
dc.date.accessioned2015-07-21T08:29:20Z-
dc.date.available2015-07-21T08:29:20Z-
dc.date.issued2015-04-01en_US
dc.identifier.issn1533-4880en_US
dc.identifier.urihttp://dx.doi.org/10.1166/jnn.2015.9208en_US
dc.identifier.urihttp://hdl.handle.net/11536/124182-
dc.description.abstractWe report a low-temperature InP p-MOS with a high capacitance density of 2.7 mu F/cm(2), low leakage current of 0.77 A/cm(2) at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-kappa TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to <1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.en_US
dc.language.isoen_USen_US
dc.subjectIndium Phosphide (InP)en_US
dc.subjectTiLaOen_US
dc.subjectEquivalent Oxide Thickness (EOT)en_US
dc.titleTiO2-Based Indium Phosphide Metal-Oxide-Semiconductor Capacitor with High Capacitance Densityen_US
dc.typeArticleen_US
dc.identifier.doi10.1166/jnn.2015.9208en_US
dc.identifier.journalJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGYen_US
dc.citation.volume15en_US
dc.citation.spage2810en_US
dc.citation.epage2813en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000347435100028en_US
dc.citation.woscount0en_US
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