完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Cheng, Chun-Hu | en_US |
dc.contributor.author | Hsu, Hsiao-Hsuan | en_US |
dc.contributor.author | Chou, Kun-I | en_US |
dc.date.accessioned | 2015-07-21T08:29:20Z | - |
dc.date.available | 2015-07-21T08:29:20Z | - |
dc.date.issued | 2015-04-01 | en_US |
dc.identifier.issn | 1533-4880 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1166/jnn.2015.9208 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124182 | - |
dc.description.abstract | We report a low-temperature InP p-MOS with a high capacitance density of 2.7 mu F/cm(2), low leakage current of 0.77 A/cm(2) at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-kappa TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to <1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Indium Phosphide (InP) | en_US |
dc.subject | TiLaO | en_US |
dc.subject | Equivalent Oxide Thickness (EOT) | en_US |
dc.title | TiO2-Based Indium Phosphide Metal-Oxide-Semiconductor Capacitor with High Capacitance Density | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1166/jnn.2015.9208 | en_US |
dc.identifier.journal | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | en_US |
dc.citation.volume | 15 | en_US |
dc.citation.spage | 2810 | en_US |
dc.citation.epage | 2813 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000347435100028 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |