標題: | An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder |
作者: | Lin, Chen-Yang Wong, Cheng-Chi Chang, Hsie-Chia 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Area-efficient;high code rate;reciprocal dual trellis;turbo decoder |
公開日期: | 1-一月-2015 |
摘要: | This brief presents an area-efficient turbo decoder based on the reciprocal dual trellis. In this brief, the radix-4 structure is introduced into the reciprocal dual trellis for throughput enhancement, and a sign-arrangement technique is developed to simplify the hardware and reduce the critical path of the recursion metric unit. To further reduce the hardware complexity, a time-multiplexing method with no degradation of throughput is also presented to save half of the extrinsic units, leading to a 15% hardware reduction of the soft-in/soft-out decoder. After implementation by CMOS 90-nm process, the proposed turbo decoder containing 600 k-gates and 152-kb SRAM can achieve 425 Mb/s with 310-mW power consumption at 8/9 code rate. The post-simulation results show that the proposed methods provide a hardware-efficient solution for turbo decoders exploiting high-code-rate operations. |
URI: | http://dx.doi.org/10.1109/TCSII.2014.2362733 http://hdl.handle.net/11536/124249 |
ISSN: | 1549-7747 |
DOI: | 10.1109/TCSII.2014.2362733 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 62 |
起始頁: | 65 |
結束頁: | 69 |
顯示於類別: | 期刊論文 |