標題: An Efficient Application Processor Architecture for Multicore Software Video Decoding
作者: Tsai, Chun-Jen
Chen, Yan-Ting
Tseng, Chien-Chih
資訊工程學系
Department of Computer Science
關鍵字: Multicore application processors;parallel video decoding;software pipeline architecture;wavefront video decoding
公開日期: 1-二月-2015
摘要: In this paper, we propose a new multicore application processor architecture that facilitates the adoption of the fine-granularity software-pipeline parallelism without causing an extra burden on the system bus. The proposed system-on-a-chip architecture can simultaneously support the traditional symmetric multiprocessor (SMP) and the proposed software-pipeline applications efficiently. The programming model of the proposed architecture is compatible with the existing SMP operating systems. For the implementation of the pipeline-based parallelism, new programmer-friendly system calls are suggested to take advantage of the new software-pipeline datapath. The proposed architecture with four reduced instruction set computing cores is implemented on an field-programmable gate array development board for verification. An Advanced Video Coding/H.264 baseline profile video decoder that explores the pipeline parallelism with dynamic pipeline-stage partitioning is implemented on the target platform to justify the benefits of the proposed architecture. Experimental results show that the adoption of the proposed pipeline datapath architecture into existing application processors enables new potentials in exploring software parallelism.
URI: http://dx.doi.org/10.1109/TCSVT.2014.2329365
http://hdl.handle.net/11536/124344
ISSN: 1051-8215
DOI: 10.1109/TCSVT.2014.2329365
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
Volume: 25
起始頁: 325
結束頁: 338
顯示於類別:期刊論文