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dc.contributor.authorChang, Chih-Weien_US
dc.contributor.authorChou, Lei-Chunen_US
dc.contributor.authorHuang, Po-Tsangen_US
dc.contributor.authorWu, Shang-Linen_US
dc.contributor.authorLee, Shih-Weien_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.contributor.authorHwang, Weien_US
dc.contributor.authorChen, Kuo-Huaen_US
dc.contributor.authorChiu, Chi-Tsungen_US
dc.contributor.authorTong, Ho-Mingen_US
dc.contributor.authorChiou, Jin-Chernen_US
dc.date.accessioned2015-07-21T08:29:00Z-
dc.date.available2015-07-21T08:29:00Z-
dc.date.issued2015-02-01en_US
dc.identifier.issn1387-2176en_US
dc.identifier.urihttp://dx.doi.org/10.1007/s10544-014-9906-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/124349-
dc.description.abstractWe present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.en_US
dc.language.isoen_USen_US
dc.subjectThrough silicon viaen_US
dc.subjectCMOS technology Neural probe arrayen_US
dc.subjectElectrodeen_US
dc.subjectHeterogeneous integrationen_US
dc.titleA double-sided, single-chip integration scheme using through-silicon-via for neural sensing applicationsen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s10544-014-9906-9en_US
dc.identifier.journalBIOMEDICAL MICRODEVICESen_US
dc.citation.volume17en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000349548200011en_US
dc.citation.woscount0en_US
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