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dc.contributor.authorDinh, Trung Anhen_US
dc.contributor.authorYamashita, Shigeruen_US
dc.contributor.authorHo, Tsung-Yien_US
dc.date.accessioned2015-07-21T08:29:25Z-
dc.date.available2015-07-21T08:29:25Z-
dc.date.issued2015-04-01en_US
dc.identifier.issn0278-0070en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCAD.2015.2394502en_US
dc.identifier.urihttp://hdl.handle.net/11536/124474-
dc.description.abstractDigital microfluidic biochips have become one of the most promising technologies for biomedical experiments. In modern microfluidic technology, reducing the number of independent control pins that reflects most of the fabrication cost, power consumption, and reliability of a microfluidic system, is a key challenge for every digital microfluidic biochip design. However, all the previous chip designs sacrifice the optimality of the problem, and only limited reduction on the number of control pins is observed. Moreover, most existing designs cannot satisfy high-throughput demand for bioassays, and thus inapplicable in practical contexts. In this paper, we propose the first optimal pin-count design scheme for digital microfluidic biochips. By integrating a very simple combinational logic circuit into the original chip, the proposed scheme can provide high-throughput for bioassays with an information-theoretic minimum number of control pins. Furthermore, to cope with the rapid growth of the chip\'s scale, we also propose a scalable and efficient heuristics to reduce the number of control pins. A logic optimization technique, which can be used to reduce the complexity of the integrated combinational logic circuit, is also presented in this paper. Experiments demonstrate that the proposed scheme can obtain much fewer number of control pins compared with the previous state-of-the-art works.en_US
dc.language.isoen_USen_US
dc.subjectDigital microfluidicsen_US
dc.subjectlogic optimizationen_US
dc.subjectpin-count reductionen_US
dc.titleAn Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochipsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCAD.2015.2394502en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMSen_US
dc.citation.volume34en_US
dc.citation.spage629en_US
dc.citation.epage641en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000351765000012en_US
dc.citation.woscount0en_US
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