完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Su, Ming-Chiuan | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Chen, Wei-Zen | en_US |
dc.date.accessioned | 2015-07-21T08:29:26Z | - |
dc.date.available | 2015-07-21T08:29:26Z | - |
dc.date.issued | 2015-04-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2014.2314740 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124477 | - |
dc.description.abstract | A low-jitter digitally controlled oscillator (DCO) with multiphase differential outputs and good linearity is presented. The DCO is composed of four differential delay cells and can achieve linear tuning over a wide frequency range. The proposed fully differential delay cell comprises logic cells in standard library and varactors. The measured rms jitter and pk-pk jitter from 2.5-GHz carrier are 2.827 and 29 ps, respectively. The power consumption is 6 mW from a 1.2 V supply. An experimental prototype is designed using 65-nm CMOS technology, and the chip area is 156 mu m x 92 mu m(2). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | All-digital | en_US |
dc.subject | differential | en_US |
dc.subject | digitally controlled oscillator (DCO) | en_US |
dc.subject | low jitter | en_US |
dc.subject | multiphase | en_US |
dc.title | A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2014.2314740 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 23 | en_US |
dc.citation.spage | 766 | en_US |
dc.citation.epage | 770 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000351751400015 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |