標題: | A Java Processor IP Design for Embedded SoC |
作者: | Tsai, Chun-Jen Kuo, Han-Wen Lin, Zigang Guo, Zi-Jing Wang, Jun-Fu 資訊工程學系 Department of Computer Science |
關鍵字: | Design;Experimentation;Performance;Java accelerator;application processor SoC;dynamic class loading;embedded systems |
公開日期: | 1-三月-2015 |
摘要: | In this article, we present a reusable Java processor IP for application processors of embedded systems. For the Java microarchitecture, we propose a low-cost stack memory design that supports a two-fold instruction folding pipeline and a low-complexity Java exception handling hardware. We also propose a mapping between the Java dynamic class loading model and the SoC platform-based design principle so that the Java core can be encapsulated as a reusable IP. To achieve this goal, a two-level method area with two on-chip circular buffers is proposed as an interface between the RISC core and the Java core. The proposed architecture is implemented on a Xilinx Virtex-5 FPGA device. Experimental results show that its performance has some advantages over other Java processors and a Java VM with JIT acceleration on a PowerPC platform. |
URI: | http://dx.doi.org/10.1145/2629649 http://hdl.handle.net/11536/124526 |
ISSN: | 1539-9087 |
DOI: | 10.1145/2629649 |
期刊: | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS |
Volume: | 14 |
顯示於類別: | 期刊論文 |