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dc.contributor.authorHuang, Zhe-Yangen_US
dc.contributor.authorChen, Chun-Chiehen_US
dc.contributor.authorHung, Chung-Chihen_US
dc.date.accessioned2015-07-21T08:28:15Z-
dc.date.available2015-07-21T08:28:15Z-
dc.date.issued2015-07-01en_US
dc.identifier.issn0253-3839en_US
dc.identifier.urihttp://dx.doi.org/10.1080/02533839.2015.1010452en_US
dc.identifier.urihttp://hdl.handle.net/11536/124771-
dc.description.abstractA low-noise amplifier (LNA) with cascode structure and shunt-peaking load is presented in this article. Both Narrow-band input impedance and wide-band input impedance LNAs were implemented in 0.18m CMOS process. Maximum power gain of the narrow-band input impedance LNA is 19.3dB; maximum power gain of the wide-band input impedance LNA is 15.3dB. Minimum noise figure of the narrow-band input impedance LNA is 3.1dB; minimum noise figure of the wide-band input impedance LNA is 3.0dB. Power consumptions including buffers are 24.5 and 25.6mW, respectively.en_US
dc.language.isoen_USen_US
dc.subjectlow-noise amplifieren_US
dc.subjectLNAen_US
dc.subjectimpedance matchingen_US
dc.subjectultra-widebanden_US
dc.titleLow-noise amplifier with narrow-band and wide-band input impedance matching designen_US
dc.typeArticleen_US
dc.identifier.doi10.1080/02533839.2015.1010452en_US
dc.identifier.journalJOURNAL OF THE CHINESE INSTITUTE OF ENGINEERSen_US
dc.citation.volume38en_US
dc.citation.spage603en_US
dc.citation.epage609en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000354874400006en_US
dc.citation.woscount0en_US
Appears in Collections:Articles


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