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dc.contributor.authorLu, Chien-Yuen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorTu, Ming-Hsienen_US
dc.contributor.authorWu, Ya-Pingen_US
dc.contributor.authorHuang, Chung-Pingen_US
dc.contributor.authorKan, Paul-Senen_US
dc.contributor.authorHuang, Huan-Shunen_US
dc.contributor.authorLee, Kuen-Dien_US
dc.contributor.authorKao, Yung-Shinen_US
dc.date.accessioned2015-07-21T08:29:40Z-
dc.date.available2015-07-21T08:29:40Z-
dc.date.issued2015-05-01en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2014.2318518en_US
dc.identifier.urihttp://hdl.handle.net/11536/124832-
dc.description.abstractThis brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.en_US
dc.language.isoen_USen_US
dc.subject9T static random access memory (SRAM)en_US
dc.subjectboosted wordlineen_US
dc.subjectline-up write-assist (LUWA)en_US
dc.subjectnegative bitlineen_US
dc.subjectsubthresholden_US
dc.subjectultralow voltageen_US
dc.titleA 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assisten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TVLSI.2014.2318518en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume23en_US
dc.citation.spage958en_US
dc.citation.epage962en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000355212000015en_US
dc.citation.woscount0en_US
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