完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lu, Chien-Yu | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Tu, Ming-Hsien | en_US |
dc.contributor.author | Wu, Ya-Ping | en_US |
dc.contributor.author | Huang, Chung-Ping | en_US |
dc.contributor.author | Kan, Paul-Sen | en_US |
dc.contributor.author | Huang, Huan-Shun | en_US |
dc.contributor.author | Lee, Kuen-Di | en_US |
dc.contributor.author | Kao, Yung-Shin | en_US |
dc.date.accessioned | 2015-07-21T08:29:40Z | - |
dc.date.available | 2015-07-21T08:29:40Z | - |
dc.date.issued | 2015-05-01 | en_US |
dc.identifier.issn | 1063-8210 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2014.2318518 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/124832 | - |
dc.description.abstract | This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 9T static random access memory (SRAM) | en_US |
dc.subject | boosted wordline | en_US |
dc.subject | line-up write-assist (LUWA) | en_US |
dc.subject | negative bitline | en_US |
dc.subject | subthreshold | en_US |
dc.subject | ultralow voltage | en_US |
dc.title | A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TVLSI.2014.2318518 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
dc.citation.volume | 23 | en_US |
dc.citation.spage | 958 | en_US |
dc.citation.epage | 962 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000355212000015 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 期刊論文 |