完整後設資料紀錄
DC 欄位語言
dc.contributor.authorWang, Wen-Chiehen_US
dc.contributor.authorWu, Chung-Yuen_US
dc.date.accessioned2014-12-08T15:17:05Z-
dc.date.available2014-12-08T15:17:05Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1000-2en_US
dc.identifier.urihttp://hdl.handle.net/11536/12490-
dc.description.abstractA new high frequency CMOS current-mode upconversion mixer is proposed to realize the transmitter frontend in the frequency band of 24 GHz. The transmitter integrates with a double-balance current-mode up-conversion mixer, an IF amplifier/repeater, a differential VCO and a differential VCO buffer/repeater. The performance of the transmitter exhibits a conversion gain of 1.3 dB, the input 1-dB compression point (P-1dB) is - 22 dBm, the input intercept 3(rd)-order compression point (P-IIP3) is - 8.75 dBm, and the output intercept 3(rd)-order compression point (P-OIP3) is - 7.44 dBm. The phase noise of the differential VCO is - 117 dBc/Hz at 10-MHz offset from 26 GHz. The proposed mixer consumes only 3.89 mW from a 1-V supply. The total power dissipation of the transmitter is 15.4 mW from 1-V supply. This chip is designed in 0.13-mu m 1P8M CMOS technology and under fabrication.en_US
dc.language.isoen_USen_US
dc.titleThe 1-V 24-GHz low-voltage low-power current-mode transmitter in 130-nm CMOS technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 PH.D RESEARCH IN MICROELECTRONICS AND ELECTRONICSen_US
dc.citation.spage49en_US
dc.citation.epage52en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000255548900013-
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