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dc.contributor.authorShrestha, Niraj Manen_US
dc.contributor.authorLin, Yueh-Chinen_US
dc.contributor.authorChang, Han-Tungen_US
dc.contributor.authorLi, Yimingen_US
dc.contributor.authorChang, Edward Yien_US
dc.date.accessioned2015-07-21T08:31:14Z-
dc.date.available2015-07-21T08:31:14Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-5433-9en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/124931-
dc.description.abstractEnhancement mode AlGaN/GaN high electron mobility transistor with p-InAlN gate is designed and successfully studied its electrical properties. Threshold voltage of the device is 1.9 V, which is required magnitude of threshold voltage for real device. Similarly, the maximum drain current is 520 mA/mm and trasconductance is 183 mS/mm, which is the record estimation for enhancement-mode (e-mode) device with recorded threshold voltage. P-InAlN layer injects hole to the barrier at higher gate voltage and results in comparatively larger drain current. Selective area etching and re-grow AlInN causes thin barrier layer beneath the gate. This recess like p-InAlN structure can reduce the concentration of 2DEG; and thus results the high magnitude of threshold voltage.en_US
dc.language.isoen_USen_US
dc.subjectEnhancement modeen_US
dc.subjectp-AlInNen_US
dc.subjectThreshold voltageen_US
dc.subject2 dimensional electron gasen_US
dc.subjectHigh electron mobility transistoren_US
dc.subjectDevice simulationen_US
dc.titleDevice Simulation of P-InAlN-Gate AlGaN/GaN High Electron Mobility Transistoren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL WORKSHOP ON COMPUTATIONAL ELECTRONICS (IWCE)en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000345736700069en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper