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dc.contributor.authorLin, Chun-Yuen_US
dc.contributor.authorChu, Li-Weien_US
dc.contributor.authorTsai, Shiang-Yuen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorSong, Ming-Hsiangen_US
dc.contributor.authorJou, Chewn-Puen_US
dc.contributor.authorLu, Tse-Huaen_US
dc.contributor.authorTseng, Jen-Chouen_US
dc.contributor.authorTsai, Ming-Hsienen_US
dc.contributor.authorHsu, Tsun-Laien_US
dc.contributor.authorHung, Ping-Fangen_US
dc.contributor.authorWei, Yu-Linen_US
dc.contributor.authorChang, Tzu-Hengen_US
dc.date.accessioned2015-07-21T08:31:29Z-
dc.date.available2015-07-21T08:31:29Z-
dc.date.issued2013-01-01en_US
dc.identifier.isbn978-1-4799-0675-8; 978-1-4799-0676-5en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/124971-
dc.description.abstractNanoscale CMOS technologies have been used to implement the radio-frequency integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of IC products. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection on circuit performances, ESD protection at input/output pads must be carefully designed. In this work, a new proposed ESD protection design has been realized in a nanoscale CMOS process. Experimental results of the test circuits have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.en_US
dc.language.isoen_USen_US
dc.titleESD Protection Design for Radio-Frequency Integrated Circuits in Nanoscale CMOS Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 13TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)en_US
dc.citation.spage241en_US
dc.citation.epage244en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000346488300055en_US
dc.citation.woscount0en_US
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