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dc.contributor.authorChen, Yu-Yuen_US
dc.contributor.authorHuang, Wen-Tsungen_US
dc.contributor.authorHsu, Sheng-Chiaen_US
dc.contributor.authorChang, Han-Tungen_US
dc.contributor.authorChen, Chieh-Yangen_US
dc.contributor.authorYang, Chin-Minen_US
dc.contributor.authorChen, Li-Wenen_US
dc.contributor.authorLi, Yimingen_US
dc.date.accessioned2015-07-21T08:31:29Z-
dc.date.available2015-07-21T08:31:29Z-
dc.date.issued2013-01-01en_US
dc.identifier.isbn978-1-4799-0675-8; 978-1-4799-0676-5en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/124972-
dc.description.abstractIn this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-kappa / metal gate n- and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations\' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.en_US
dc.language.isoen_USen_US
dc.titleStatistical Device Simulation of Intrinsic Parameter Fluctuation in 16-nm-Gate N- and P-type Bulk FinFETsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 13TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO)en_US
dc.citation.spage442en_US
dc.citation.epage445en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000346488300099en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper