元件佈局相關之寄生效應和參數萃取方法應用於奈米射頻CMOS模擬及雜訊分析

Abstract

在本論文中，元件佈局效應，包含淺溝槽隔離層與應力工程如CESL所產生之應力都將會被探討。為了得到更高的操作頻率與更低的雜訊，多閘指元件已被廣泛應用在射頻電路設計，但是淺溝槽隔離層所產生的應力對於等效載子遷移率與轉導之影響，卻顯現出基本的問題。另一方面，為了降低閘極電阻，多閘指元件被設計為更窄的閘指寬度與更多的閘指數目，使得三維雜散電容與電阻成為另一個關鍵的問題。上述因子導致複雜的佈局效應，並為多閘指元件設計與建模帶來了艱鉅的挑戰。首先，本論文建立了一個命名為傳輸線模型之源極電阻萃取方法，並且證明了其精確性，促進了精確的等效載子遷移率之萃取。此外，本論文也應用了修正的Y-method來獨立萃取閘極電阻(Rg)與閘極矽晶電阻(Rpoly)，此方法可以得到可靠的佈局與偏壓相關性，並且促進最大振盪頻率與高頻雜訊之精確建模和佈局最佳化。 佈局效應對於低頻雜訊的影響包含了頻域的閃爍雜訊(flicker noise)與時域的隨機電報雜訊(random telegraph noise)，前者已證實遵循1/f之趨勢，但是 顯現強烈的VGS依賴性。在閘極氧化層中之不均勻缺陷分布可以解釋這個有趣的結果。我們的實驗結果顯示，較高的VGS會導致 大於1，這表示低頻缺陷扮演了主要的角色。而更窄的閘指寬度與更大的閘指數目可以導致更低的閃爍雜訊，此結果可以顯示等效總寬度上升的優勢大過了淺溝槽隔離層應力與介面缺陷的影響。小型的元件如單一閘指元件之隨機電報雜訊量測結果，顯示出複雜的多階層汲極電流變化特性，反應了在單一能階或多能階缺陷上有不同的電子數目。在強反轉情況下，隨機電報雜訊造成之門檻電壓變動大約小於來自隨機佈植變動一個數量級。然而，隨機電報雜訊對於操作在小於門檻電壓之區域的影響仍然存在著一些問題值得未來投入更多的研究探討。 最後，在第五章我們建立一個完整的高頻CMOS模型以模擬高頻特性及高頻雜訊對元件佈局效性影響。結合本實驗室特有的參數萃取方法(此方法已得到美國專利認證US patent 8,691,599 B2)，Rs, Rg 以及Rpoly 的萃取參數，更能幫助我們做模型校正及增進模擬的精確性。不過，最初始的BSIM-4對於元件佈局效應，顯示出許多根本的問題，例如、臨界電壓和載子遷移率等模型，但最大問題是對於高頻雜訊的模擬，有相當大的誤差。欲應用其熱雜訊模型於高頻雜訊模擬必須大幅的校正，且僅是停留在數值模擬以求貼近其特性曲線。因而，一改良的熱雜訊模型成為在未來的研究重點與努力方向，必須能精確預測元件佈局效應。

In this thesis, layout dependent effects, incorporating process induced stress from STI and strain engineering like CESL induced tensile stress will be investigated. The impact of STI compressive stress on effective mobility eff and transconductance gm appears as the basic problem in multi-finger devices, which have been widely used in RF circuits design for higher fT, fMAX, and lower noise. 3-D parasitic capacitances and resistances emerge as another critical factor, which becomes more serious in multi-finger devices with smaller finger width (WF) and larger finger number (NF) for gate resistance (Rg) reduction. The mentioned factors lead to a complicated layout dependent effects and brings a tough challenge to multi-finger devices design and modeling for RF and analog circuits application. For the first time, a new method for Rs extraction, namely distributed transmission line (TML) model, has been developed in this thesis and proven with required accuracy to match the layout dependence of gm and facilitate an accurate eff extraction. Moreover, a modified Y-method has been implemented to realize a separate extraction of Rg and Rpoly, which can yield reliable layout and biases dependence and facilitate an accurate modeling and layout optimization for fMAX and RF noise. The impact of layout dependent effects on low frequency noises will cover flicker noise in frequency domain and random telegraph noise (RTN) in time domain. The former one has been known, following a function of 1/f but reveals a strong VGS dependence in the exponent. The interesting results can be explained by non-uniform trap distribution in the gate oxide. In our experimental, the higher VGS leading to  >1 suggests that low frequency traps play a dominant role. The smaller WF and larger NF leads to lower flicker noise (SID/IDS2) appears as one more interesting finding and suggests the benefit from an increase of Weff, which may dominate the impact from STI transverse stress and interface traps (Nt). RTN measured from miniaturized devices, such as single finger and narrow-OD and multi-OD devices in this thesis, reveal a complex ID_RTN characteristic with multiple levels of current fluctuation amplitude (ID), which reflect different electron numbers in a single trap or multiple trap levels. The VT variation caused by RTN under strong inversion condition is around one order smaller than those originated from random dopant fluctuation (RDF). However, RTN in subthreshold region appears as an open question and deserve more research effort in the future. Finally, a compact RF CMOS device model has been built in chapter 5, to realize an extensive simulation for layout dependent effects on high frequency performance and noise. Our proprietary device parameters extraction method (US patent 8,691,599 B2) combining the new methods developed in this thesis for Rs, Rg, Rpoly extraction may help facilitate model calibration and simulation accuracy. Unfortunately, the default BSIM-4 exposes a bunch of fundamental problems in layout dependent effects on basic device parameters and models like VT and mobility, and what’s even worse a dramatic deviation from the measured RF noise. An extensive calibration is mandatory for thermal noise model implemented in BSIM-4 but stays as a curve fitting approach at current phase. An improved thermal noise model with proven accuracy in layout dependent effects deserve an extensive research effort in the future.