俱溫度補償數位控制振盪器之全數位頻率合成器設計

Abstract

本論文針對全域非同步區域同步(Globally-Asynchronous Locally-Synchronous, GALS)所需要的區域時脈，提出一個快速鎖定並且對溫度變異有抵抗能力的振盪源。 首先，我們利用全數位頻率合成迴路，產生數位控制振盪器輸出目標頻率所需的控制碼，如此可以解決製程參數變異的影響。接著，我們將迴路切斷並且固定振盪控制碼，此時之開迴路數位振盪器即為GALS系統需要的區域時脈。值得一提的是，頻率合成器僅在頻率鎖定的過程中需要短暫的外部參考時脈，當頻率鎖定之後，可以停止外部的參考時脈輸入，這在系統晶片中對於矽面積與功耗的消耗上面，可以有相當大的節省。 然而，開迴路振盪器會受到電壓與溫度變異的影響產生頻率偏移，因此我們針對溫度變異提出一個補償電路，使振盪器對於溫度變異有較佳的抵抗能力。 為了使全數位頻率合成迴路達成快速鎖定的目的，我們採用假位法(Regula Falsi)的演算法在追鎖頻率上面做快速鎖定，當輸出頻率與目標頻率比較靠近時，將迴路切到頻寬較大的數位濾波器，待迴路鎖定之後，再將濾波器的頻寬切小。利用假位法以及改變濾波器頻寬的方法，經由量測證實，全數位頻率合成器最慢可以在11個時脈周期之內完成鎖定頻率的目標。 為了補償數位控制振盪器在開迴路之下因為溫度變異而產生的輸出頻率偏移，我們利用常數轉導偏壓電路使延遲單元的電晶體特性與溫度變異較不敏感，此補償方法亦可以在不同控制電壓之下發揮作用。 此電路使用TSMC 0.18μm CMOS製程實現，核心面積為0.239 〖mm〗^2，整體面積為0.895 〖mm〗^2。經由量測驗證其輸出頻率範圍在1.85 GHz至3 GHz內皆可正常操作。在2.4 GHz輸出頻率時，能在7個參考時脈內完成頻率鎖定，方均根時脈抖動值為0.545 %，峰對峰時脈抖動值為4.334 %，相位雜訊為-84.09(dBc/Hz)@1MHz Offset，功率消耗為17.74 mW。 開迴路之俱溫度補償數位控制振盪器在輸出頻率為2.4 GHz時，有效溫度係數為186 ppm/℃，溫度變化為-40℃至100℃。

This thesis presents a design of the clock generator for the application of GALS (Globally-Asynchronous Locally-Synchronous) system. The clock source has the ability of fast-locking and alleviating the impact of output frequency deviation due to temperature variations. The all-digital frequency-locked loop generates the output frequency of the digitally controlled oscillator as the target frequency first by means of negative feedback. Then the feedback loop was disconnected and the oscillator tuning word was kept so that the oscillator outputs the target frequency at free-running to serve as the clock source that the GALS system needs. By doing so, the clock generator does not need a continuous reference clock. Hence, the reference clock generator can then be shutdown. SoC system can save much of the silicon area and its power, which makes it much more attractive. Since the open-loop oscillator's output frequency is sensitive to the supply voltage and temperature variations, we propose a temperature compensated circuit design to make it less sensitive to temperature variations. To achieve fast lock-in, the Regula Falsi method has been used in the design of the all-digital frequency-locked loop. When the output frequency is closed to the expected frequency, the loop switches to a closed loop with a digital filter. Initially, the filter is set to have a wide bandwidth for a faster locking process. After the output frequency is locked to the expected frequency, the filter's bandwidth is set to a smaller one for stable output frequency. Measurement results show that the lock-in process is less than 11 cycles at its worst. To address the output frequency deviations of the free-running digitally controlled oscillator due to the temperature variations, a constant-gm circuit is used to alleviate the parameter change of the transistors in the delay cells. In particular, the proposed method works under different control voltages. A test chip has been implemented in TSMC 0.18μm CMOS technology. The core area is 0.239 〖mm〗^2 and the whole-chip area with bonding pads is 0.895 〖mm〗^2. Measurement results show that the chip can operate correctly when the output frequency is between 1.85 GHz and 3.0 GHz. When the output frequency is 2.4 GHz, the lock-in time needs 7 reference cycles. The measured rms jitter is 0.545% unit-interval (U.I.) and the peak-to-peak jitter is 4.334% unit-interval (U.I.). The phase noise spectral density at 1 MHz offset is measured to be -84.09(dBc/Hz). The power consumption of the core circuits is 17.74 mW. The measured effective temperature coefficient of the free-running digitally controlled oscillator is 186 ppm/℃ in the range between -40℃ and 100℃.